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Searched refs:VC4_SET_FIELD (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_state.c511 (VC4_SET_FIELD(magfilter_map[cso->mag_img_filter], in vc4_create_sampler_state()
513 VC4_SET_FIELD(minfilter_map[cso->min_mip_filter * 2 + in vc4_create_sampler_state()
516 VC4_SET_FIELD(translate_wrap(cso->wrap_s, either_nearest), in vc4_create_sampler_state()
518 VC4_SET_FIELD(translate_wrap(cso->wrap_t, either_nearest), in vc4_create_sampler_state()
617 (VC4_SET_FIELD((rsc->slices[0].offset + in vc4_create_sampler_view()
620 VC4_SET_FIELD(rsc->vc4_format & 15, VC4_TEX_P0_TYPE) | in vc4_create_sampler_view()
621 VC4_SET_FIELD(so->force_first_level ? in vc4_create_sampler_view()
625 VC4_SET_FIELD(cso->target == PIPE_TEXTURE_CUBE, in vc4_create_sampler_view()
628 (VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) | in vc4_create_sampler_view()
629 VC4_SET_FIELD(prsc->height0 & 2047, VC4_TEX_P1_HEIGHT) | in vc4_create_sampler_view()
[all …]
Dvc4_job.c298 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_ZS, in vc4_submit_setup_rcl_surface()
303 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_COLOR, in vc4_submit_setup_rcl_surface()
305 VC4_SET_FIELD(vc4_rt_format_is_565(psurf->format) ? in vc4_submit_setup_rcl_surface()
311 VC4_SET_FIELD(surf->tiling, in vc4_submit_setup_rcl_surface()
338 VC4_SET_FIELD(vc4_rt_format_is_565(surf->base.format) ? in vc4_submit_setup_rcl_render_config_surface()
342 VC4_SET_FIELD(surf->tiling, in vc4_submit_setup_rcl_render_config_surface()
Dvc4_uniforms.c69 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE, in write_texture_p2()
71 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) | in write_texture_p2()
72 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD)); in write_texture_p2()
/external/igt-gpu-tools/tests/
Dvc4_lookup_fail.c54 .bits = VC4_SET_FIELD(VC4_RENDER_CONFIG_FORMAT_RGBA8888,
/external/mesa3d/src/gallium/drivers/vc4/kernel/
Dvc4_packet.h131 #define VC4_SET_FIELD(value, field) \ macro
Dvc4_validate.c379 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
381 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
Dvc4_render_cl.c77 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, in vc4_store_before_load()
/external/libdrm/vc4/
Dvc4_packet.h128 #define VC4_SET_FIELD(value, field) \ macro
/external/igt-gpu-tools/lib/
Dvc4_packet.h128 #define VC4_SET_FIELD(value, field) \ macro
Digt_vc4.c94 .bits = VC4_SET_FIELD(VC4_RENDER_CONFIG_FORMAT_RGBA8888, in igt_vc4_get_cleared_bo()