| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | vfcmp.ll | 28 ; ole is implemented with VCGE
63 ; ugt is implemented with VCGE/VMVN
75 ; ult is implemented with VCGE/VMVN
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
|
| D | vicmp.ll | 6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vfcmp.ll | 28 ; ole is implemented with VCGE
63 ; ugt is implemented with VCGE/VMVN
75 ; ult is implemented with VCGE/VMVN
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
|
| D | vicmp.ll | 6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
|
| /external/vixl/test/aarch32/config/ |
| D | cond-dt-drt-drd-drn-drm-float.json | 37 "Vcge", // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A2
38 // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T2
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 1373 VCGE/VCGEQ output:
1374 VCGE/VCGEQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, ff, }
1375 VCGE/VCGEQ:1:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1376 VCGE/VCGEQ:2:result_uint32x2 [] = { ffffffff, ffffffff, }
1377 VCGE/VCGEQ:3:result_uint8x8 [] = { 0, 0, 0, ff, ff, ff, ff, ff, }
1378 VCGE/VCGEQ:4:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1379 VCGE/VCGEQ:5:result_uint32x2 [] = { 0, ffffffff, }
1380 VCGE/VCGEQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, ff, }
1381 VCGE/VCGEQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, ffff, }
1382 VCGE/VCGEQ:8:result_uint32x4 [] = { 0, 0, ffffffff, ffffffff, }
[all …]
|
| D | ref-rvct-neon.txt | 1465 VCGE/VCGEQ output:
1466 VCGE/VCGEQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, ff, }
1467 VCGE/VCGEQ:1:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1468 VCGE/VCGEQ:2:result_uint32x2 [] = { ffffffff, ffffffff, }
1469 VCGE/VCGEQ:3:result_uint8x8 [] = { 0, 0, 0, ff, ff, ff, ff, ff, }
1470 VCGE/VCGEQ:4:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1471 VCGE/VCGEQ:5:result_uint32x2 [] = { 0, ffffffff, }
1472 VCGE/VCGEQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, ff, }
1473 VCGE/VCGEQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, ffff, }
1474 VCGE/VCGEQ:8:result_uint32x4 [] = { 0, 0, ffffffff, ffffffff, }
[all …]
|
| D | ref-rvct-all.txt | 1465 VCGE/VCGEQ output:
1466 VCGE/VCGEQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, ff, }
1467 VCGE/VCGEQ:1:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1468 VCGE/VCGEQ:2:result_uint32x2 [] = { ffffffff, ffffffff, }
1469 VCGE/VCGEQ:3:result_uint8x8 [] = { 0, 0, 0, ff, ff, ff, ff, ff, }
1470 VCGE/VCGEQ:4:result_uint16x4 [] = { 0, 0, ffff, ffff, }
1471 VCGE/VCGEQ:5:result_uint32x2 [] = { 0, ffffffff, }
1472 VCGE/VCGEQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, ff, }
1473 VCGE/VCGEQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, ffff, }
1474 VCGE/VCGEQ:8:result_uint32x4 [] = { 0, 0, ffffffff, ffffffff, }
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 98 VCGE, // Vector compare greater than or equal. enumerator
|
| D | ARMScheduleSwift.td | 555 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
|
| D | ARMISelLowering.cpp | 1173 case ARMISD::VCGE: return "ARMISD::VCGE"; in getTargetNodeName()
4904 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
4908 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; in LowerVSETCC()
4925 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
4937 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
4975 if (Opc == ARMISD::VCGE) in LowerVSETCC()
4987 case ARMISD::VCGE: in LowerVSETCC()
|
| D | ARMScheduleA9.td | 2411 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
|
| D | ARMInstrNEON.td | 497 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
4729 // VCGE : Vector Compare Greater Than or Equal
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 794 (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>;
|
| D | ARMScheduleSwift.td | 571 "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
|
| D | ARMScheduleA57.td | 1004 (instregex "VCEQ", "VCGE", "VCGT", "VCLE", "VTST", "VCLT")>;
|
| D | ARMScheduleA9.td | 2434 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
|
| D | ARMInstrNEON.td | 5101 // VCGE : Vector Compare Greater Than or Equal
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 794 (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>;
|
| D | ARMScheduleSwift.td | 571 "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
|
| D | ARMScheduleA57.td | 1011 (instregex "VCEQ", "VCGE", "VCGT", "VCLE", "VTST", "VCLT")>;
|
| D | ARMScheduleA9.td | 2434 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
|
| D | ARMInstrNEON.td | 5108 // VCGE : Vector Compare Greater Than or Equal
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 552 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
|
| /external/llvm-project/clang/include/clang/Basic/ |
| D | arm_neon.td | 352 def VCGE : SOpInst<"vcge", "U..", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
|