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Searched refs:VCGT (Results 1 – 25 of 35) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/ARM/
Dvfcmp.ll17 ; olt is implemented with VCGT
39 ; uge is implemented with VCGT/VMVN
51 ; ule is implemented with VCGT/VMVN
87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
101 ; one is implemented with VCGT/VCGT/VORR
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
Dvicmp.ll6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
/external/llvm/test/CodeGen/ARM/
Dvfcmp.ll17 ; olt is implemented with VCGT
39 ; uge is implemented with VCGT/VMVN
51 ; ule is implemented with VCGT/VMVN
87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
101 ; one is implemented with VCGT/VCGT/VORR
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
Dvicmp.ll6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
/external/libhevc/common/arm/
Dihevc_sao_edge_offset_class1.s142 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
157 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
172 VCGT.U8 Q11,Q9,Q15 @II vcgtq_u8(pu1_cur_row, pu1_top_row)
236 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
287 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
299 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row)
311 VCGT.U8 Q11,Q9,Q15 @II vcgtq_u8(pu1_cur_row, pu1_next_row)
355 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row)
356 VCGT.U8 Q7,Q9,Q5 @vcltq_u8(pu1_cur_row, pu1_next_row)
Dihevc_sao_edge_offset_class1_chroma.s146 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
161 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
176 VCGT.U8 Q11,Q9,Q15 @II vcgtq_u8(pu1_cur_row, pu1_top_row)
248 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
304 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
316 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row)
328 VCGT.U8 Q11,Q9,Q15 @II vcgtq_u8(pu1_cur_row, pu1_next_row)
385 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row)
386 VCGT.U8 Q7,Q9,Q5 @vcltq_u8(pu1_cur_row, pu1_next_row)
Dihevc_sao_edge_offset_class0_chroma.s174 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
188 VCGT.U8 Q13,Q15,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
202 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
217 VCGT.U8 Q13,Q15,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
337 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
351 VCGT.U8 Q13,Q15,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
362 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
380 VCGT.U8 Q13,Q15,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
Dihevc_sao_edge_offset_class0.s167 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
184 VCGT.U8 Q15,Q13,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
195 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
213 VCGT.U8 Q15,Q13,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
307 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
315 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
Dihevc_sao_edge_offset_class2.s257 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
302 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
369 VCGT.U8 Q12,Q6,Q11 @II vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
384 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
470 VCGT.U8 Q5,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
569 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
616 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
697 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
747 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
Dihevc_sao_edge_offset_class3.s272 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
317 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
394 VCGT.U8 Q12,Q6,Q9 @II vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
419 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
508 VCGT.U8 Q12,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
610 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
657 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
752 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
799 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
Dihevc_sao_edge_offset_class3_chroma.s340 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
404 VCGT.U8 Q10,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
487 VCGT.U8 Q11,Q6,Q14 @II vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
527 VCGT.U8 Q11,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
638 VCGT.U8 Q10,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
732 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
810 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
919 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
986 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
Dihevc_sao_edge_offset_class2_chroma.s350 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
412 VCGT.U8 Q10,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
486 VCGT.U8 Q11,Q6,Q14 @II vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
537 VCGT.U8 Q10,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
631 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
742 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
788 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
893 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
938 VCGT.U8 Q11,Q6,Q9 @vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
/external/vixl/test/aarch32/config/
Dcond-dt-drt-drd-drn-drm-float.json39 "Vcgt", // VCGT{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A2
40 // VCGT{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T2
/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt1425 VCGT/VCGTQ output:
1426 VCGT/VCGTQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, 0, ff, }
1427 VCGT/VCGTQ:1:result_uint16x4 [] = { 0, 0, 0, ffff, }
1428 VCGT/VCGTQ:2:result_uint32x2 [] = { 0, ffffffff, }
1429 VCGT/VCGTQ:3:result_uint8x8 [] = { 0, 0, 0, 0, ff, ff, ff, ff, }
1430 VCGT/VCGTQ:4:result_uint16x4 [] = { 0, 0, 0, ffff, }
1431 VCGT/VCGTQ:5:result_uint32x2 [] = { 0, 0, }
1432 VCGT/VCGTQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, }
1433 VCGT/VCGTQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, 0, ffff, }
1434 VCGT/VCGTQ:8:result_uint32x4 [] = { 0, 0, 0, ffffffff, }
[all …]
Dref-rvct-neon.txt1517 VCGT/VCGTQ output:
1518 VCGT/VCGTQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, 0, ff, }
1519 VCGT/VCGTQ:1:result_uint16x4 [] = { 0, 0, 0, ffff, }
1520 VCGT/VCGTQ:2:result_uint32x2 [] = { 0, ffffffff, }
1521 VCGT/VCGTQ:3:result_uint8x8 [] = { 0, 0, 0, 0, ff, ff, ff, ff, }
1522 VCGT/VCGTQ:4:result_uint16x4 [] = { 0, 0, 0, ffff, }
1523 VCGT/VCGTQ:5:result_uint32x2 [] = { 0, 0, }
1524 VCGT/VCGTQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, }
1525 VCGT/VCGTQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, 0, ffff, }
1526 VCGT/VCGTQ:8:result_uint32x4 [] = { 0, 0, 0, ffffffff, }
[all …]
Dref-rvct-all.txt1517 VCGT/VCGTQ output:
1518 VCGT/VCGTQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, 0, ff, }
1519 VCGT/VCGTQ:1:result_uint16x4 [] = { 0, 0, 0, ffff, }
1520 VCGT/VCGTQ:2:result_uint32x2 [] = { 0, ffffffff, }
1521 VCGT/VCGTQ:3:result_uint8x8 [] = { 0, 0, 0, 0, ff, ff, ff, ff, }
1522 VCGT/VCGTQ:4:result_uint16x4 [] = { 0, 0, 0, ffff, }
1523 VCGT/VCGTQ:5:result_uint32x2 [] = { 0, 0, }
1524 VCGT/VCGTQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, }
1525 VCGT/VCGTQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, 0, ffff, }
1526 VCGT/VCGTQ:8:result_uint32x4 [] = { 0, 0, 0, ffffffff, }
[all …]
/external/llvm/lib/Target/ARM/
DARMISelLowering.h102 VCGT, // Vector compare greater than. enumerator
DARMISelLowering.cpp1177 case ARMISD::VCGT: return "ARMISD::VCGT"; in getTargetNodeName()
4900 case ISD::SETGT: Opc = ARMISD::VCGT; break; in LowerVSETCC()
4906 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; in LowerVSETCC()
4915 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC()
4916 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
4924 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC()
4935 case ISD::SETGT: Opc = ARMISD::VCGT; break; in LowerVSETCC()
4977 else if (Opc == ARMISD::VCGT) in LowerVSETCC()
4991 case ARMISD::VCGT: in LowerVSETCC()
DARMScheduleSwift.td555 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
/external/llvm-project/llvm/lib/Target/ARM/
DARMScheduleR52.td794 (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>;
DARMScheduleSwift.td571 "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
DARMScheduleA57.td1004 (instregex "VCEQ", "VCGE", "VCGT", "VCLE", "VTST", "VCLT")>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleR52.td794 (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>;
DARMScheduleSwift.td571 "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
DARMScheduleA57.td1011 (instregex "VCEQ", "VCGE", "VCGT", "VCLE", "VTST", "VCLT")>;

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