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Searched refs:VDUPLANE (Results 1 – 11 of 11) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMISelLowering.h149 VDUPLANE, enumerator
DARMISelLowering.cpp1206 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; in getTargetNodeName()
5762 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
5767 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
6154 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, in GeneratePerfectShuffle()
6255 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, in LowerVECTOR_SHUFFLE()
10149 if (User->getOpcode() != ARMISD::VDUPLANE || in CombineVLDDUP()
11048 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); in PerformDAGCombine()
DARMInstrNEON.td563 // VDUPLANE can produce a quad-register result from a double-register source,
565 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.h190 VDUPLANE, enumerator
DARMISelLowering.cpp1642 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; in getTargetNodeName()
7272 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
7277 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
7705 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, in GeneratePerfectShuffle()
7984 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, in LowerVECTOR_SHUFFLE()
13337 if (User->getOpcode() != ARMISD::VDUPLANE || in CombineVLDDUP()
14642 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); in PerformDAGCombine()
DARMInstrInfo.td250 // VDUPLANE can produce a quad-register result from a double-register source,
252 def ARMvduplane : SDNode<"ARMISD::VDUPLANE",
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.h193 VDUPLANE, enumerator
DARMISelLowering.cpp1708 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; in getTargetNodeName()
7569 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
7574 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
8011 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, in GeneratePerfectShuffle()
8290 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, in LowerVECTOR_SHUFFLE()
14422 if (User->getOpcode() != ARMISD::VDUPLANE || in CombineVLDDUP()
16314 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI, Subtarget); in PerformDAGCombine()
DARMInstrInfo.td253 // VDUPLANE can produce a quad-register result from a double-register source,
255 def ARMvduplane : SDNode<"ARMISD::VDUPLANE",
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc6042 /* 12363*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
6101 /* 12493*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
6126 /* 12542*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
6147 /* 12584*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
6171 /* 12632*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
6192 /* 12674*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
6218 /* 12723*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
6239 /* 12764*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
6265 /* 12812*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
6290 /* 12860*/ OPC_CheckOpcode, TARGET_VAL(ARMISD::VDUPLANE),
[all …]
DARMGenFastISel.inc5542 // FastEmit functions for ARMISD::VDUPLANE.
6506 case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri(VT, RetVT, Op0, Op0IsKill, imm1);
7637 // FastEmit functions for ARMISD::VDUPLANE.
7679 …case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(VT, RetVT, Op0, …