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Searched refs:VE (Results 1 – 25 of 441) sorted by relevance

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/external/llvm-project/llvm/lib/Target/VE/Disassembler/
DVEDisassembler.cpp57 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
58 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
59 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
60 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
61 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
62 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
63 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
64 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
65 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
66 VE::SW63};
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/external/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
DVEAsmBackend.cpp36 case VE::fixup_ve_hi32: in adjustFixupValue()
37 case VE::fixup_ve_pc_hi32: in adjustFixupValue()
38 case VE::fixup_ve_got_hi32: in adjustFixupValue()
39 case VE::fixup_ve_gotoff_hi32: in adjustFixupValue()
40 case VE::fixup_ve_plt_hi32: in adjustFixupValue()
41 case VE::fixup_ve_tls_gd_hi32: in adjustFixupValue()
42 case VE::fixup_ve_tpoff_hi32: in adjustFixupValue()
44 case VE::fixup_ve_reflong: in adjustFixupValue()
45 case VE::fixup_ve_lo32: in adjustFixupValue()
46 case VE::fixup_ve_pc_lo32: in adjustFixupValue()
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DVEELFObjectWriter.cpp59 case VE::fixup_ve_pc_hi32: in getRelocType()
61 case VE::fixup_ve_pc_lo32: in getRelocType()
77 case VE::fixup_ve_reflong: in getRelocType()
79 case VE::fixup_ve_hi32: in getRelocType()
81 case VE::fixup_ve_lo32: in getRelocType()
83 case VE::fixup_ve_pc_hi32: in getRelocType()
85 case VE::fixup_ve_pc_lo32: in getRelocType()
87 case VE::fixup_ve_got_hi32: in getRelocType()
89 case VE::fixup_ve_got_lo32: in getRelocType()
91 case VE::fixup_ve_gotoff_hi32: in getRelocType()
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DVEMCExpr.cpp137 VE::Fixups VEMCExpr::getFixupKind(VEMCExpr::VariantKind Kind) { in getFixupKind()
142 return VE::fixup_ve_reflong; in getFixupKind()
144 return VE::fixup_ve_hi32; in getFixupKind()
146 return VE::fixup_ve_lo32; in getFixupKind()
148 return VE::fixup_ve_pc_hi32; in getFixupKind()
150 return VE::fixup_ve_pc_lo32; in getFixupKind()
152 return VE::fixup_ve_got_hi32; in getFixupKind()
154 return VE::fixup_ve_got_lo32; in getFixupKind()
156 return VE::fixup_ve_gotoff_hi32; in getFixupKind()
158 return VE::fixup_ve_gotoff_lo32; in getFixupKind()
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/external/llvm-project/llvm/lib/Target/VE/
DVEFrameLowering.cpp152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
153 .addReg(VE::SX11) in emitPrologueInsns()
156 .addReg(VE::SX9); in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
158 .addReg(VE::SX11) in emitPrologueInsns()
161 .addReg(VE::SX10); in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
165 .addReg(VE::SX11) in emitPrologueInsns()
168 .addReg(VE::SX15); in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
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DVEInstrInfo.cpp39 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {} in VEInstrInfo()
98 using namespace llvm::VE; in isUncondBranchOpcode()
113 using namespace llvm::VE; in isCondBranchOpcode()
125 using namespace llvm::VE; in isIndirectBranchOpcode()
238 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
254 opc[0] = VE::BRCFWir; in insertBranch()
255 opc[1] = VE::BRCFWrr; in insertBranch()
257 opc[0] = VE::BRCFLir; in insertBranch()
258 opc[1] = VE::BRCFLrr; in insertBranch()
262 opc[0] = VE::BRCFSir; in insertBranch()
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DVERegisterInfo.cpp33 VERegisterInfo::VERegisterInfo() : VEGenRegisterInfo(VE::SX10) {} in VERegisterInfo()
67 VE::SX8, // Stack limit in getReservedRegs()
68 VE::SX9, // Frame pointer in getReservedRegs()
69 VE::SX10, // Link register (return address) in getReservedRegs()
70 VE::SX11, // Stack pointer in getReservedRegs()
73 VE::SX12, // Outer register in getReservedRegs()
74 VE::SX13, // Id register for dynamic linker in getReservedRegs()
76 VE::SX14, // Thread pointer in getReservedRegs()
77 VE::SX15, // Global offset table register in getReservedRegs()
78 VE::SX16, // Procedure linkage table register in getReservedRegs()
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DVEFrameLowering.h60 {VE::SX17, 40}, {VE::SX18, 48}, {VE::SX19, 56}, {VE::SX20, 64}, in getCalleeSavedSpillSlots()
61 {VE::SX21, 72}, {VE::SX22, 80}, {VE::SX23, 88}, {VE::SX24, 96}, in getCalleeSavedSpillSlots()
62 {VE::SX25, 104}, {VE::SX26, 112}, {VE::SX27, 120}, {VE::SX28, 128}, in getCalleeSavedSpillSlots()
63 {VE::SX29, 136}, {VE::SX30, 144}, {VE::SX31, 152}, {VE::SX32, 160}, in getCalleeSavedSpillSlots()
64 {VE::SX33, 168}}; in getCalleeSavedSpillSlots()
DVERegisterInfo.td1 //===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===//
10 // Declarations that describe the VE register file
18 let Namespace = "VE";
26 let Namespace = "VE";
34 let Namespace = "VE";
44 let Namespace = "VE";
49 let Namespace = "VE" in {
77 def MISC : RegisterClass<"VE", [i64], 64,
95 def VLS : RegisterClass<"VE", [i32], 64, (add VL)>;
168 def I32 : RegisterClass<"VE", [i32], 32,
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DVE.td1 //===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===//
19 // VE Subtarget features.
36 // Use both VE register name matcher to accept "S0~S63" register names
43 // VE processors supported.
61 def VE : Target {
DVEAsmPrinter.cpp86 SICInst.setOpcode(VE::SIC); in emitSIC()
94 BSICInst.setOpcode(VE::BSICrii); in emitBSIC()
106 LEAInst.setOpcode(VE::LEAzii); in emitLEAzzi()
118 LEASLInst.setOpcode(VE::LEASLzii); in emitLEASLzzi()
130 LEAInst.setOpcode(VE::LEAzii); in emitLEAzii()
143 LEASLInst.setOpcode(VE::LEASLrri); in emitLEASLrri()
164 emitBinary(OutStreamer, VE::ANDrm, RS1, Imm, RD, STI); in emitANDrm()
203 MCOperand RegGOT = MCOperand::createReg(VE::SX15); // GOT in lowerGETGOTAndEmitMCInsts()
204 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETGOTAndEmitMCInsts()
252 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETFunPLTAndEmitMCInsts()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
DVEFrameLowering.cpp51 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
52 .addReg(VE::SX11) in emitPrologueInsns()
54 .addReg(VE::SX9); in emitPrologueInsns()
55 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
56 .addReg(VE::SX11) in emitPrologueInsns()
58 .addReg(VE::SX10); in emitPrologueInsns()
59 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
60 .addReg(VE::SX11) in emitPrologueInsns()
62 .addReg(VE::SX15); in emitPrologueInsns()
63 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
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DVEInstrInfo.cpp38 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI(), in VEInstrInfo()
43 case VE::EXTEND_STACK: { in expandPostRAPseudo()
46 case VE::EXTEND_STACK_GUARD: { in expandPostRAPseudo()
94 BuildMI(BB, dl, TII.get(VE::BCRLrr)) in expandExtendStackPseudo()
96 .addReg(VE::SX11) // %sp in expandExtendStackPseudo()
97 .addReg(VE::SX8) // %sl in expandExtendStackPseudo()
105 BuildMI(BB, dl, TII.get(VE::LDSri), VE::SX61) in expandExtendStackPseudo()
106 .addReg(VE::SX14) in expandExtendStackPseudo()
108 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62) in expandExtendStackPseudo()
109 .addReg(VE::SX0) in expandExtendStackPseudo()
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DVEFrameLowering.h52 {VE::SX17, 40}, {VE::SX18, 48}, {VE::SX19, 56}, {VE::SX20, 64}, in getCalleeSavedSpillSlots()
53 {VE::SX21, 72}, {VE::SX22, 80}, {VE::SX23, 88}, {VE::SX24, 96}, in getCalleeSavedSpillSlots()
54 {VE::SX25, 104}, {VE::SX26, 112}, {VE::SX27, 120}, {VE::SX28, 128}, in getCalleeSavedSpillSlots()
55 {VE::SX29, 136}, {VE::SX30, 144}, {VE::SX31, 152}, {VE::SX32, 160}, in getCalleeSavedSpillSlots()
56 {VE::SX33, 168}}; in getCalleeSavedSpillSlots()
DVERegisterInfo.cpp33 VERegisterInfo::VERegisterInfo() : VEGenRegisterInfo(VE::SX10) {} in VERegisterInfo()
51 Reserved.set(VE::SX8); // stack limit in getReservedRegs()
52 Reserved.set(VE::SX9); // frame pointer in getReservedRegs()
53 Reserved.set(VE::SX10); // link register (return address) in getReservedRegs()
54 Reserved.set(VE::SX11); // stack pointer in getReservedRegs()
56 Reserved.set(VE::SX12); // outer register in getReservedRegs()
57 Reserved.set(VE::SX13); // id register for dynamic linker in getReservedRegs()
59 Reserved.set(VE::SX14); // thread pointer in getReservedRegs()
60 Reserved.set(VE::SX15); // global offset table register in getReservedRegs()
61 Reserved.set(VE::SX16); // procedure linkage table register in getReservedRegs()
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DVEISelLowering.cpp78 .Case("sp", VE::SX11) // Stack pointer in getRegisterByName()
79 .Case("fp", VE::SX9) // Frame pointer in getRegisterByName()
80 .Case("sl", VE::SX8) // Stack limit in getRegisterByName()
81 .Case("lr", VE::SX10) // Link regsiter in getRegisterByName()
82 .Case("tp", VE::SX14) // Thread pointer in getRegisterByName()
83 .Case("outer", VE::SX12) // Outer regiser in getRegisterByName()
84 .Case("info", VE::SX17) // Info area register in getRegisterByName()
85 .Case("got", VE::SX15) // Global offset table register in getRegisterByName()
86 .Case("plt", VE::SX16) // Procedure linkage table register in getRegisterByName()
111 addRegisterClass(MVT::i64, &VE::I64RegClass); in VETargetLowering()
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DVE.td1 //===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===//
19 // VE Subtarget features.
33 // VE processors supported.
51 def VE : Target {
DLLVMBuild.txt1 ;===- ./lib/Target/VE/LLVMBuild.txt ----------------------------*- Conf -*--===;
22 name = VE
30 parent = VE
34 add_to_library_groups = VE
DVERegisterInfo.td1 //===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===//
10 // Declarations that describe the VE register file
16 let Namespace = "VE";
36 def I64 : RegisterClass<"VE", [i64], 64,
DVECallingConv.td1 //===-- VECallingConv.td - Calling Conventions VE ----------*- tablegen -*-===//
9 // This describes the calling conventions for the VE architectures.
14 // Aurora VE
/external/llvm-project/llvm/lib/Target/VE/AsmParser/
DVEAsmParser.cpp99 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
100 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
101 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
102 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
103 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
104 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
105 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
106 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
107 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
108 VE::SW63};
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/external/llvm/lib/Bitcode/Writer/
DBitcodeWriter.cpp111 ValueEnumerator VE; member in __anon3744d1e50111::ModuleBitcodeWriter
128 : BitcodeWriter(Buffer), M(*M), VE(*M, ShouldPreserveUseListOrder), in ModuleBitcodeWriter()
684 const std::vector<AttributeSet> &AttrGrps = VE.getAttributeGroups(); in writeAttributeGroupTable()
695 Record.push_back(VE.getAttributeGroupID(A)); in writeAttributeGroupTable()
731 const std::vector<AttributeSet> &Attrs = VE.getAttributes(); in writeAttributeTable()
740 Record.push_back(VE.getAttributeGroupID(A.getSlotAttributes(i))); in writeAttributeTable()
751 const ValueEnumerator::TypeList &TypeList = VE.getTypes(); in writeTypeTable()
756 uint64_t NumBits = VE.computeBitsRequiredForTypeIndicies(); in writeTypeTable()
839 TypeVals.push_back(VE.getTypeID(PTy->getElementType())); in writeTypeTable()
850 TypeVals.push_back(VE.getTypeID(FT->getReturnType())); in writeTypeTable()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Bitcode/Writer/
DBitcodeWriter.cpp159 ValueEnumerator VE; member in __anonb6dd13c70111::ModuleBitcodeWriterBase
184 VE(M, ShouldPreserveUseListOrder), Index(Index) { in ModuleBitcodeWriterBase()
190 GlobalValueId = VE.getValues().size(); in ModuleBitcodeWriterBase()
238 return VE.getValueID(VI.getValue()); in getValueId()
740 VE.getAttributeGroups(); in writeAttributeGroupTable()
749 Record.push_back(VE.getAttributeGroupID(Pair)); in writeAttributeGroupTable()
777 Record.push_back(VE.getTypeID(Attr.getValueAsType())); in writeAttributeGroupTable()
789 const std::vector<AttributeList> &Attrs = VE.getAttributeLists(); in writeAttributeTable()
800 Record.push_back(VE.getAttributeGroupID({i, AS})); in writeAttributeTable()
812 const ValueEnumerator::TypeList &TypeList = VE.getTypes(); in writeTypeTable()
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/external/llvm-project/llvm/lib/Bitcode/Writer/
DBitcodeWriter.cpp162 ValueEnumerator VE; member in __anonace5aa530111::ModuleBitcodeWriterBase
187 VE(M, ShouldPreserveUseListOrder), Index(Index) { in ModuleBitcodeWriterBase()
193 GlobalValueId = VE.getValues().size(); in ModuleBitcodeWriterBase()
241 return VE.getValueID(VI.getValue()); in getValueId()
765 VE.getAttributeGroups(); in writeAttributeGroupTable()
774 Record.push_back(VE.getAttributeGroupID(Pair)); in writeAttributeGroupTable()
802 Record.push_back(VE.getTypeID(Attr.getValueAsType())); in writeAttributeGroupTable()
814 const std::vector<AttributeList> &Attrs = VE.getAttributeLists(); in writeAttributeTable()
825 Record.push_back(VE.getAttributeGroupID({i, AS})); in writeAttributeTable()
837 const ValueEnumerator::TypeList &TypeList = VE.getTypes(); in writeTypeTable()
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/external/llvm-project/llvm/test/CodeGen/VE/Scalar/
Dsjlj_except.ll2 …n-model=sjlj --print-after=sjljehprepare < %s || true) 2>&1 | FileCheck --check-prefix=CHECK-VE %s
7 ; CHECK-VE: *** IR Dump After SJLJ Exception Handling preparation ***
8 ; CHECK-VE-NEXT: define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality i8* bitcast (i3…
9 ; CHECK-VE-NEXT: entry:
10 ; CHECK-VE-NEXT: %fn_context = alloca { i8*, i64, [4 x i64], i8*, i8*, [5 x i8*] }, align 8
11 ; CHECK-VE-NEXT: %arg.tmp = select i1 true, i32 %arg, i32 undef
12 ; CHECK-VE-NEXT: %pers_fn_gep = getelementptr { i8*, i64, [4 x i64], i8*, i8*, [5 x i8*] }, { i8*…

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