| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-reductions.ll | 85 ; CHECK: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_FMIN [[COPY]](<4 x s32>)
86 ; CHECK: $s0 = COPY [[VECREDUCE_FMIN]](s32)
97 ; CHECK: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = nnan G_VECREDUCE_FMIN [[COPY]](<4 x s32>)
98 ; CHECK: $s0 = COPY [[VECREDUCE_FMIN]](s32)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 933 VECREDUCE_FMAX, VECREDUCE_FMIN, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1146 VECREDUCE_FMIN, enumerator
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 487 case ISD::VECREDUCE_FMIN: in LegalizeOp()
883 case ISD::VECREDUCE_FMIN: in Expand()
|
| D | SelectionDAGDumper.cpp | 471 case ISD::VECREDUCE_FMIN: return "vecreduce_fmin"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 139 case ISD::VECREDUCE_FMIN: in SoftenFloatResult()
2260 case ISD::VECREDUCE_FMIN: in PromoteFloatResult()
2623 case ISD::VECREDUCE_FMIN: in SoftPromoteHalfResult()
|
| D | LegalizeVectorTypes.cpp | 628 case ISD::VECREDUCE_FMIN: in ScalarizeVectorOperand()
2129 case ISD::VECREDUCE_FMIN: in SplitVectorOperand()
4401 case ISD::VECREDUCE_FMIN: in WidenVectorOperand()
|
| D | LegalizeDAG.cpp | 1176 case ISD::VECREDUCE_FMIN: in LegalizeOp()
3949 case ISD::VECREDUCE_FMIN: in ExpandNode()
|
| D | SelectionDAG.cpp | 375 case ISD::VECREDUCE_FMIN: in getVecReduceBaseOpcode()
|
| D | SelectionDAGBuilder.cpp | 9082 Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1, SDFlags); in visitVectorReduce()
|
| D | DAGCombiner.cpp | 1748 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N); in visit()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 450 case ISD::VECREDUCE_FMIN: return "vecreduce_fmin"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 486 case ISD::VECREDUCE_FMIN: in LegalizeOp()
990 case ISD::VECREDUCE_FMIN: in Expand()
|
| D | LegalizeVectorTypes.cpp | 616 case ISD::VECREDUCE_FMIN: in ScalarizeVectorOperand()
1996 case ISD::VECREDUCE_FMIN: in SplitVectorOperand()
2084 case ISD::VECREDUCE_FMIN: in SplitVecOp_VECREDUCE()
4237 case ISD::VECREDUCE_FMIN: in WidenVectorOperand()
4721 case ISD::VECREDUCE_FMIN: in WidenVecOp_VECREDUCE()
|
| D | LegalizeDAG.cpp | 1160 case ISD::VECREDUCE_FMIN: in LegalizeOp()
3809 case ISD::VECREDUCE_FMIN: in ExpandNode()
|
| D | TargetLowering.cpp | 7625 case ISD::VECREDUCE_FMIN: in expandVecReduce()
|
| D | SelectionDAGBuilder.cpp | 9011 Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1); in visitVectorReduce()
|
| D | DAGCombiner.cpp | 1625 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N); in visit()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 724 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 842 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 996 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in AArch64TargetLowering()
1367 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in addTypeForFixedLengthSVE()
4292 case ISD::VECREDUCE_FMIN: in LowerOperation()
10239 case ISD::VECREDUCE_FMIN: in LowerVECREDUCE()
10265 case ISD::VECREDUCE_FMIN: { in LowerVECREDUCE()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 358 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in addMVEVectorTypes()
381 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom); in addMVEVectorTypes()
385 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom); in addMVEVectorTypes()
9538 case ISD::VECREDUCE_FMIN: BaseOpcode = ISD::FMINNUM; break; in LowerVecReduce()
9806 case ISD::VECREDUCE_FMIN: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 798 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in AArch64TargetLowering()
3274 case ISD::VECREDUCE_FMIN: in LowerOperation()
8564 case ISD::VECREDUCE_FMIN: { in LowerVECREDUCE()
|