Searched refs:VECREDUCE_FMUL (Results 1 – 21 of 21) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 931 VECREDUCE_FADD, VECREDUCE_FMUL, enumerator
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| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-reductions.ll | 57 …; CHECK: [[VECREDUCE_FMUL:%[0-9]+]]:_(s64) = reassoc G_VECREDUCE_FMUL [[CONCAT_VECTORS]](<4 x s6…
58 ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = reassoc G_FMUL [[COPY]], [[VECREDUCE_FMUL]]
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1143 VECREDUCE_FMUL, enumerator
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 485 case ISD::VECREDUCE_FMUL: in LegalizeOp()
881 case ISD::VECREDUCE_FMUL: in Expand()
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| D | SelectionDAGDumper.cpp | 459 case ISD::VECREDUCE_FMUL: return "vecreduce_fmul"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 138 case ISD::VECREDUCE_FMUL: in SoftenFloatResult()
2259 case ISD::VECREDUCE_FMUL: in PromoteFloatResult()
2622 case ISD::VECREDUCE_FMUL: in SoftPromoteHalfResult()
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| D | LegalizeVectorTypes.cpp | 617 case ISD::VECREDUCE_FMUL: in ScalarizeVectorOperand()
2118 case ISD::VECREDUCE_FMUL: in SplitVectorOperand()
4390 case ISD::VECREDUCE_FMUL: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1165 case ISD::VECREDUCE_FMUL: in LegalizeOp()
3938 case ISD::VECREDUCE_FMUL: in ExpandNode()
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| D | SelectionDAG.cpp | 352 case ISD::VECREDUCE_FMUL: in getVecReduceBaseOpcode()
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| D | SelectionDAGBuilder.cpp | 9046 DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2, SDFlags), in visitVectorReduce()
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| D | DAGCombiner.cpp | 1737 case ISD::VECREDUCE_FMUL: in visit()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 438 case ISD::VECREDUCE_FMUL: return "vecreduce_fmul"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 484 case ISD::VECREDUCE_FMUL: in LegalizeOp()
988 case ISD::VECREDUCE_FMUL: in Expand()
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| D | LegalizeVectorTypes.cpp | 605 case ISD::VECREDUCE_FMUL: in ScalarizeVectorOperand()
1985 case ISD::VECREDUCE_FMUL: in SplitVectorOperand()
2071 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break; in SplitVecOp_VECREDUCE()
4226 case ISD::VECREDUCE_FMUL: in WidenVectorOperand()
4714 case ISD::VECREDUCE_FMUL: in WidenVecOp_VECREDUCE()
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| D | LegalizeDAG.cpp | 1149 case ISD::VECREDUCE_FMUL: in LegalizeOp()
3798 case ISD::VECREDUCE_FMUL: in ExpandNode()
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| D | TargetLowering.cpp | 7612 case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break; in expandVecReduce()
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| D | SelectionDAGBuilder.cpp | 8976 DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2)); in visitVectorReduce()
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| D | DAGCombiner.cpp | 1614 case ISD::VECREDUCE_FMUL: in visit()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 713 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand); in initActions()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 831 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand); in initActions()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 357 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom); in addMVEVectorTypes()
380 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom); in addMVEVectorTypes()
384 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom); in addMVEVectorTypes()
9532 case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break; in LowerVecReduce()
9805 case ISD::VECREDUCE_FMUL: in LowerOperation()
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