| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator
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| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-reductions.ll | 184 ; CHECK: [[VECREDUCE_SMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_SMAX [[COPY]](<4 x s32>)
185 ; CHECK: $w0 = COPY [[VECREDUCE_SMAX]](s32)
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1155 VECREDUCE_SMAX, enumerator
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 480 case ISD::VECREDUCE_SMAX: in LegalizeOp()
876 case ISD::VECREDUCE_SMAX: in Expand()
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| D | SelectionDAGDumper.cpp | 466 case ISD::VECREDUCE_SMAX: return "vecreduce_smax"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 204 case ISD::VECREDUCE_SMAX: in PromoteIntegerResult()
1522 case ISD::VECREDUCE_SMAX: in PromoteIntegerOperand()
1970 case ISD::VECREDUCE_SMAX: in PromoteIntOp_VECREDUCE()
2161 case ISD::VECREDUCE_SMAX: in ExpandIntegerResult()
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| D | LegalizeVectorTypes.cpp | 623 case ISD::VECREDUCE_SMAX: in ScalarizeVectorOperand()
2124 case ISD::VECREDUCE_SMAX: in SplitVectorOperand()
4396 case ISD::VECREDUCE_SMAX: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1171 case ISD::VECREDUCE_SMAX: in LegalizeOp()
3944 case ISD::VECREDUCE_SMAX: in ExpandNode()
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| D | SelectionDAG.cpp | 365 case ISD::VECREDUCE_SMAX: in getVecReduceBaseOpcode()
4747 case ISD::VECREDUCE_SMAX: in getNode()
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| D | SelectionDAGBuilder.cpp | 9067 Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1); in visitVectorReduce()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 445 case ISD::VECREDUCE_SMAX: return "vecreduce_smax"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 479 case ISD::VECREDUCE_SMAX: in LegalizeOp()
983 case ISD::VECREDUCE_SMAX: in Expand()
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| D | LegalizeVectorTypes.cpp | 611 case ISD::VECREDUCE_SMAX: in ScalarizeVectorOperand()
1991 case ISD::VECREDUCE_SMAX: in SplitVectorOperand()
2077 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break; in SplitVecOp_VECREDUCE()
4232 case ISD::VECREDUCE_SMAX: in WidenVectorOperand()
4703 case ISD::VECREDUCE_SMAX: in WidenVecOp_VECREDUCE()
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| D | LegalizeIntegerTypes.cpp | 195 case ISD::VECREDUCE_SMAX: in PromoteIntegerResult()
1318 case ISD::VECREDUCE_SMAX: in PromoteIntegerOperand()
1743 case ISD::VECREDUCE_SMAX: in PromoteIntOp_VECREDUCE()
1924 case ISD::VECREDUCE_SMAX: in ExpandIntegerResult()
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| D | LegalizeDAG.cpp | 1155 case ISD::VECREDUCE_SMAX: in LegalizeOp()
3804 case ISD::VECREDUCE_SMAX: in ExpandNode()
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| D | TargetLowering.cpp | 7618 case ISD::VECREDUCE_SMAX: BaseOpcode = ISD::SMAX; break; in expandVecReduce()
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| D | SelectionDAGBuilder.cpp | 8996 Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1); in visitVectorReduce()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 719 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 837 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1001 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in AArch64TargetLowering()
1094 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in AArch64TargetLowering()
1207 setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom); in AArch64TargetLowering()
1369 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in addTypeForFixedLengthSVE()
4286 case ISD::VECREDUCE_SMAX: in LowerOperation()
10225 case ISD::VECREDUCE_SMAX: in LowerVECREDUCE()
10251 case ISD::VECREDUCE_SMAX: in LowerVECREDUCE()
15838 case ISD::VECREDUCE_SMAX: in ReplaceNodeResults()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 428 def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>;
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 435 def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 784 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in AArch64TargetLowering()
3269 case ISD::VECREDUCE_SMAX: in LowerOperation()
8549 case ISD::VECREDUCE_SMAX: in LowerVECREDUCE()
12933 case ISD::VECREDUCE_SMAX: in ReplaceNodeResults()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 297 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal); in addMVEVectorTypes()
12168 } else if ((TrueVal->getOpcode() == ISD::VECREDUCE_SMAX || in PerformSELECTCombine()
12169 FalseVal->getOpcode() == ISD::VECREDUCE_SMAX) && in PerformSELECTCombine()
12182 case ISD::VECREDUCE_SMAX: in PerformSELECTCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 291 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal); in addMVEVectorTypes()
|