| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator
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| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-reductions.ll | 208 ; CHECK: [[VECREDUCE_UMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_UMAX [[COPY]](<4 x s32>)
209 ; CHECK: $w0 = COPY [[VECREDUCE_UMAX]](s32)
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1157 VECREDUCE_UMAX, enumerator
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 482 case ISD::VECREDUCE_UMAX: in LegalizeOp()
878 case ISD::VECREDUCE_UMAX: in Expand()
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| D | SelectionDAGDumper.cpp | 468 case ISD::VECREDUCE_UMAX: return "vecreduce_umax"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 206 case ISD::VECREDUCE_UMAX: in PromoteIntegerResult()
1524 case ISD::VECREDUCE_UMAX: in PromoteIntegerOperand()
1974 case ISD::VECREDUCE_UMAX: in PromoteIntOp_VECREDUCE()
2163 case ISD::VECREDUCE_UMAX: in ExpandIntegerResult()
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| D | LegalizeVectorTypes.cpp | 625 case ISD::VECREDUCE_UMAX: in ScalarizeVectorOperand()
2126 case ISD::VECREDUCE_UMAX: in SplitVectorOperand()
4398 case ISD::VECREDUCE_UMAX: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1173 case ISD::VECREDUCE_UMAX: in LegalizeOp()
3946 case ISD::VECREDUCE_UMAX: in ExpandNode()
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| D | SelectionDAG.cpp | 369 case ISD::VECREDUCE_UMAX: in getVecReduceBaseOpcode()
4743 case ISD::VECREDUCE_UMAX: in getNode()
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| D | DAGCombiner.cpp | 1745 case ISD::VECREDUCE_UMAX: in visit()
21164 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX; in visitVECREDUCE()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 447 case ISD::VECREDUCE_UMAX: return "vecreduce_umax"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 481 case ISD::VECREDUCE_UMAX: in LegalizeOp()
985 case ISD::VECREDUCE_UMAX: in Expand()
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| D | LegalizeVectorTypes.cpp | 613 case ISD::VECREDUCE_UMAX: in ScalarizeVectorOperand()
1993 case ISD::VECREDUCE_UMAX: in SplitVectorOperand()
2079 case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break; in SplitVecOp_VECREDUCE()
4234 case ISD::VECREDUCE_UMAX: in WidenVectorOperand()
4693 case ISD::VECREDUCE_UMAX: in WidenVecOp_VECREDUCE()
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| D | LegalizeIntegerTypes.cpp | 197 case ISD::VECREDUCE_UMAX: in PromoteIntegerResult()
1320 case ISD::VECREDUCE_UMAX: in PromoteIntegerOperand()
1747 case ISD::VECREDUCE_UMAX: in PromoteIntOp_VECREDUCE()
1926 case ISD::VECREDUCE_UMAX: in ExpandIntegerResult()
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| D | LegalizeDAG.cpp | 1157 case ISD::VECREDUCE_UMAX: in LegalizeOp()
3806 case ISD::VECREDUCE_UMAX: in ExpandNode()
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| D | TargetLowering.cpp | 7620 case ISD::VECREDUCE_UMAX: BaseOpcode = ISD::UMAX; break; in expandVecReduce()
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| D | DAGCombiner.cpp | 1622 case ISD::VECREDUCE_UMAX: in visit()
19757 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX; in visitVECREDUCE()
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| D | SelectionDAGBuilder.cpp | 9002 Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1); in visitVectorReduce()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 721 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 839 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1003 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); in AArch64TargetLowering()
1092 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); in AArch64TargetLowering()
1209 setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom); in AArch64TargetLowering()
1371 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); in addTypeForFixedLengthSVE()
4288 case ISD::VECREDUCE_UMAX: in LowerOperation()
10229 case ISD::VECREDUCE_UMAX: in LowerVECREDUCE()
10255 case ISD::VECREDUCE_UMAX: in LowerVECREDUCE()
15840 case ISD::VECREDUCE_UMAX: in ReplaceNodeResults()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 429 def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>;
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 436 def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 786 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); in AArch64TargetLowering()
3271 case ISD::VECREDUCE_UMAX: in LowerOperation()
8553 case ISD::VECREDUCE_UMAX: in LowerVECREDUCE()
12935 case ISD::VECREDUCE_UMAX: in ReplaceNodeResults()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 298 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal); in addMVEVectorTypes()
12162 } else if ((TrueVal->getOpcode() == ISD::VECREDUCE_UMAX || in PerformSELECTCombine()
12163 FalseVal->getOpcode() == ISD::VECREDUCE_UMAX) && in PerformSELECTCombine()
12181 case ISD::VECREDUCE_UMAX: in PerformSELECTCombine()
|