| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator
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| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-reductions.ll | 220 ; CHECK: [[VECREDUCE_UMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_UMIN [[COPY]](<4 x s32>)
221 ; CHECK: $w0 = COPY [[VECREDUCE_UMIN]](s32)
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1158 VECREDUCE_UMIN, enumerator
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 483 case ISD::VECREDUCE_UMIN: in LegalizeOp()
879 case ISD::VECREDUCE_UMIN: in Expand()
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| D | SelectionDAGDumper.cpp | 469 case ISD::VECREDUCE_UMIN: return "vecreduce_umin"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 207 case ISD::VECREDUCE_UMIN: in PromoteIntegerResult()
1525 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break; in PromoteIntegerOperand()
1975 case ISD::VECREDUCE_UMIN: in PromoteIntOp_VECREDUCE()
2164 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | LegalizeVectorTypes.cpp | 626 case ISD::VECREDUCE_UMIN: in ScalarizeVectorOperand()
2127 case ISD::VECREDUCE_UMIN: in SplitVectorOperand()
4399 case ISD::VECREDUCE_UMIN: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1174 case ISD::VECREDUCE_UMIN: in LegalizeOp()
3947 case ISD::VECREDUCE_UMIN: in ExpandNode()
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| D | SelectionDAG.cpp | 371 case ISD::VECREDUCE_UMIN: in getVecReduceBaseOpcode()
4748 case ISD::VECREDUCE_UMIN: in getNode()
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| D | DAGCombiner.cpp | 1746 case ISD::VECREDUCE_UMIN: in visit()
21164 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX; in visitVECREDUCE()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 448 case ISD::VECREDUCE_UMIN: return "vecreduce_umin"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 482 case ISD::VECREDUCE_UMIN: in LegalizeOp()
986 case ISD::VECREDUCE_UMIN: in Expand()
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| D | LegalizeVectorTypes.cpp | 614 case ISD::VECREDUCE_UMIN: in ScalarizeVectorOperand()
1994 case ISD::VECREDUCE_UMIN: in SplitVectorOperand()
2080 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break; in SplitVecOp_VECREDUCE()
4235 case ISD::VECREDUCE_UMIN: in WidenVectorOperand()
4700 case ISD::VECREDUCE_UMIN: in WidenVecOp_VECREDUCE()
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| D | LegalizeIntegerTypes.cpp | 198 case ISD::VECREDUCE_UMIN: in PromoteIntegerResult()
1321 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break; in PromoteIntegerOperand()
1748 case ISD::VECREDUCE_UMIN: in PromoteIntOp_VECREDUCE()
1927 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | LegalizeDAG.cpp | 1158 case ISD::VECREDUCE_UMIN: in LegalizeOp()
3807 case ISD::VECREDUCE_UMIN: in ExpandNode()
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| D | TargetLowering.cpp | 7621 case ISD::VECREDUCE_UMIN: BaseOpcode = ISD::UMIN; break; in expandVecReduce()
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| D | DAGCombiner.cpp | 1623 case ISD::VECREDUCE_UMIN: in visit()
19757 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX; in visitVECREDUCE()
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| D | SelectionDAGBuilder.cpp | 9005 Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1); in visitVectorReduce()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 722 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand); in initActions()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 840 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand); in initActions()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1004 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); in AArch64TargetLowering()
1091 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); in AArch64TargetLowering()
1210 setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
1372 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); in addTypeForFixedLengthSVE()
4289 case ISD::VECREDUCE_UMIN: in LowerOperation()
10231 case ISD::VECREDUCE_UMIN: in LowerVECREDUCE()
10257 case ISD::VECREDUCE_UMIN: in LowerVECREDUCE()
15841 case ISD::VECREDUCE_UMIN: in ReplaceNodeResults()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 431 def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>;
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| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 438 def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 787 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); in AArch64TargetLowering()
3272 case ISD::VECREDUCE_UMIN: in LowerOperation()
8555 case ISD::VECREDUCE_UMIN: in LowerVECREDUCE()
12936 case ISD::VECREDUCE_UMIN: in ReplaceNodeResults()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 300 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal); in addMVEVectorTypes()
12150 if ((TrueVal->getOpcode() == ISD::VECREDUCE_UMIN || in PerformSELECTCombine()
12151 FalseVal->getOpcode() == ISD::VECREDUCE_UMIN) && in PerformSELECTCombine()
12179 case ISD::VECREDUCE_UMIN: in PerformSELECTCombine()
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