| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 33 field bit VINTRP = 0;
154 let TSFlags{13} = VINTRP;
350 let VINTRP = 1;
351 // VINTRP instructions read parameter values from LDS, but these parameter
|
| D | SIDefines.h | 40 VINTRP = 1 << 13, enumerator
|
| D | SIInstrInfo.h | 605 return MI.getDesc().TSFlags & SIInstrFlags::VINTRP; in isVINTRP()
609 return get(Opcode).TSFlags & SIInstrFlags::VINTRP; in isVINTRP()
|
| D | SIInstructions.td | 25 // VINTRP Instructions
33 // FIXME: Specify SchedRW for VINTRP instructions.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 33 field bit VINTRP = 0;
146 let TSFlags{13} = VINTRP;
344 let VINTRP = 1;
345 // VINTRP instructions read parameter values from LDS, but these parameter
|
| D | SIDefines.h | 40 VINTRP = 1 << 13, enumerator
|
| D | SIInstrInfo.h | 575 return MI.getDesc().TSFlags & SIInstrFlags::VINTRP; in isVINTRP()
579 return get(Opcode).TSFlags & SIInstrFlags::VINTRP; in isVINTRP()
|
| D | SIInstructions.td | 31 // VINTRP Instructions
39 // FIXME: Specify SchedRW for VINTRP insturctions.
|
| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 58 VINTRP = 1 << 12 variable in Format
129 elif self == Format.VINTRP:
939 VINTRP = { variable
945 for (code, name) in VINTRP:
946 opcode(name, code, code, code, Format.VINTRP)
|
| D | aco_insert_NOPs.cpp | 216 (pred->format == Format::VINTRP && Vintrp) || in handle_raw_hazard_internal()
356 } else if (instr->isVALU() || instr->format == Format::VINTRP) { in handle_instruction_gfx6()
411 if (instr->format == Format::VINTRP || in handle_instruction_gfx6()
|
| D | aco_opt_value_numbering.cpp | 95 case Format::VINTRP: in operator ()()
238 case Format::VINTRP: { in operator ()()
|
| D | README-ISA.md | 81 ## VINTRP encoding
146 ### VINTRP followed by a read with `v_readfirstlane` or `v_readlane`
|
| D | aco_validate.cpp | 118 else if ((uint32_t)base_format & (uint32_t)Format::VINTRP) { in validate_ir()
128 base_format = Format::VINTRP; in validate_ir()
138 base_format == Format::VINTRP, in validate_ir()
|
| D | aco_assembler.cpp | 286 case Format::VINTRP: { in emit_instruction()
561 } else if ((uint16_t) instr->format & (uint16_t) Format::VINTRP) { in emit_instruction()
|
| D | aco_print_ir.cpp | 348 case Format::VINTRP: { in print_instr_format_specific()
|
| D | aco_ir.h | 106 VINTRP = 1 << 12, enumerator
|
| /external/llvm-project/llvm/docs/ |
| D | AMDGPUModifierSyntax.rst | 961 VINTRP Modifiers
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 1427 // VINTRP Instructions
1432 // FIXME: Specify SchedRW for VINTRP insturctions.
|
| /external/mesa3d/docs/relnotes/ |
| D | 20.2.0.rst | 4309 - aco: validate v_interp_*_f16 as VOP3 instructions instead of VINTRP
4310 - aco: emit v_interp_*_f16 instructions as VOP3 instead of VINTRP
|
| D | 19.3.0.rst | 3283 - aco: Support GFX10 VINTRP in aco_assembler.
|
| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX7.rst | 636 VINTRP section in Instructions
|
| D | AMDGPUAsmGFX8.rst | 666 VINTRP section in Instructions
|
| D | AMDGPUAsmGFX9.rst | 840 VINTRP section in Instructions
|
| D | AMDGPUAsmGFX10.rst | 1325 VINTRP section in Instructions
|