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1 #ifndef STATE_3D_XML
2 #define STATE_3D_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
9 
10 The rules-ng-ng source files this header was generated from are:
11 - state.xml     (  26877 bytes, from 2020-10-28 12:56:03)
12 - common.xml    (  35468 bytes, from 2020-10-28 12:56:03)
13 - common_3d.xml (  15058 bytes, from 2020-10-28 12:56:03)
14 - state_hi.xml  (  34803 bytes, from 2020-10-28 12:56:03)
15 - copyright.xml (   1597 bytes, from 2020-10-28 12:56:03)
16 - state_2d.xml  (  51552 bytes, from 2020-10-28 12:56:03)
17 - state_3d.xml  (  84002 bytes, from 2020-11-01 11:28:08)
18 - state_blt.xml (  14252 bytes, from 2020-10-28 12:56:03)
19 - state_vg.xml  (   5975 bytes, from 2020-10-28 12:56:03)
20 
21 Copyright (C) 2012-2020 by the following authors:
22 - Wladimir J. van der Laan <laanwj@gmail.com>
23 - Christian Gmeiner <christian.gmeiner@gmail.com>
24 - Lucas Stach <l.stach@pengutronix.de>
25 - Russell King <rmk@arm.linux.org.uk>
26 
27 Permission is hereby granted, free of charge, to any person obtaining a
28 copy of this software and associated documentation files (the "Software"),
29 to deal in the Software without restriction, including without limitation
30 the rights to use, copy, modify, merge, publish, distribute, sub license,
31 and/or sell copies of the Software, and to permit persons to whom the
32 Software is furnished to do so, subject to the following conditions:
33 
34 The above copyright notice and this permission notice (including the
35 next paragraph) shall be included in all copies or substantial portions
36 of the Software.
37 
38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
41 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
44 DEALINGS IN THE SOFTWARE.
45 */
46 
47 
48 #define STENCIL_OP_KEEP						0x00000000
49 #define STENCIL_OP_ZERO						0x00000001
50 #define STENCIL_OP_REPLACE					0x00000002
51 #define STENCIL_OP_INCR						0x00000003
52 #define STENCIL_OP_DECR						0x00000004
53 #define STENCIL_OP_INVERT					0x00000005
54 #define STENCIL_OP_INCR_WRAP					0x00000006
55 #define STENCIL_OP_DECR_WRAP					0x00000007
56 #define BLEND_EQ_ADD						0x00000000
57 #define BLEND_EQ_SUBTRACT					0x00000001
58 #define BLEND_EQ_REVERSE_SUBTRACT				0x00000002
59 #define BLEND_EQ_MIN						0x00000003
60 #define BLEND_EQ_MAX						0x00000004
61 #define BLEND_FUNC_ZERO						0x00000000
62 #define BLEND_FUNC_ONE						0x00000001
63 #define BLEND_FUNC_SRC_COLOR					0x00000002
64 #define BLEND_FUNC_ONE_MINUS_SRC_COLOR				0x00000003
65 #define BLEND_FUNC_SRC_ALPHA					0x00000004
66 #define BLEND_FUNC_ONE_MINUS_SRC_ALPHA				0x00000005
67 #define BLEND_FUNC_DST_ALPHA					0x00000006
68 #define BLEND_FUNC_ONE_MINUS_DST_ALPHA				0x00000007
69 #define BLEND_FUNC_DST_COLOR					0x00000008
70 #define BLEND_FUNC_ONE_MINUS_DST_COLOR				0x00000009
71 #define BLEND_FUNC_SRC_ALPHA_SATURATE				0x0000000a
72 #define BLEND_FUNC_CONSTANT_ALPHA				0x0000000b
73 #define BLEND_FUNC_ONE_MINUS_CONSTANT_ALPHA			0x0000000c
74 #define BLEND_FUNC_CONSTANT_COLOR				0x0000000d
75 #define BLEND_FUNC_ONE_MINUS_CONSTANT_COLOR			0x0000000e
76 #define RS_FORMAT_X4R4G4B4					0x00000000
77 #define RS_FORMAT_A4R4G4B4					0x00000001
78 #define RS_FORMAT_X1R5G5B5					0x00000002
79 #define RS_FORMAT_A1R5G5B5					0x00000003
80 #define RS_FORMAT_R5G6B5					0x00000004
81 #define RS_FORMAT_X8R8G8B8					0x00000005
82 #define RS_FORMAT_A8R8G8B8					0x00000006
83 #define RS_FORMAT_YUY2						0x00000007
84 #define RS_FORMAT_64BPP_CLEAR					0x00000015
85 #define PE_FORMAT_X4R4G4B4					0x00000000
86 #define PE_FORMAT_A4R4G4B4					0x00000001
87 #define PE_FORMAT_X1R5G5B5					0x00000002
88 #define PE_FORMAT_A1R5G5B5					0x00000003
89 #define PE_FORMAT_R5G6B5					0x00000004
90 #define PE_FORMAT_X8R8G8B8					0x00000005
91 #define PE_FORMAT_A8R8G8B8					0x00000006
92 #define PE_FORMAT_YUY2						0x00000007
93 #define PE_FORMAT_A8						0x00000010
94 #define PE_FORMAT_R16F						0x00000011
95 #define PE_FORMAT_G16R16F					0x00000012
96 #define PE_FORMAT_A16B16G16R16F					0x00000013
97 #define PE_FORMAT_R32F						0x00000014
98 #define PE_FORMAT_G32R32F					0x00000015
99 #define PE_FORMAT_A2B10G10R10					0x00000016
100 #define PE_FORMAT_R8I						0x00000017
101 #define PE_FORMAT_G8R8I						0x00000018
102 #define PE_FORMAT_A8B8G8R8I					0x00000019
103 #define PE_FORMAT_R16I						0x0000001a
104 #define PE_FORMAT_G16R16I					0x0000001b
105 #define PE_FORMAT_A16B16G16R16I					0x0000001c
106 #define PE_FORMAT_B10G11R11F					0x0000001d
107 #define PE_FORMAT_A2B10G10R10UI					0x0000001e
108 #define PE_FORMAT_G8R8						0x0000001f
109 #define PE_FORMAT_R8						0x00000023
110 #define LOGIC_OP_CLEAR						0x00000000
111 #define LOGIC_OP_NOR						0x00000001
112 #define LOGIC_OP_AND_INVERTED					0x00000002
113 #define LOGIC_OP_COPY_INVERTED					0x00000003
114 #define LOGIC_OP_AND_REVERSE					0x00000004
115 #define LOGIC_OP_INVERT						0x00000005
116 #define LOGIC_OP_XOR						0x00000006
117 #define LOGIC_OP_NAND						0x00000007
118 #define LOGIC_OP_AND						0x00000008
119 #define LOGIC_OP_EQUIV						0x00000009
120 #define LOGIC_OP_NOOP						0x0000000a
121 #define LOGIC_OP_OR_INVERTED					0x0000000b
122 #define LOGIC_OP_COPY						0x0000000c
123 #define LOGIC_OP_OR_REVERSE					0x0000000d
124 #define LOGIC_OP_OR						0x0000000e
125 #define LOGIC_OP_SET						0x0000000f
126 #define COLOR_OUTPUT_MODE_NORMAL				0x00000000
127 #define COLOR_OUTPUT_MODE_A2B10G10R10UI				0x00000001
128 #define COLOR_OUTPUT_MODE_UIF32					0x00000002
129 #define COLOR_OUTPUT_MODE_U8					0x00000003
130 #define COLOR_OUTPUT_MODE_U16					0x00000004
131 #define COLOR_OUTPUT_MODE_I8					0x00000005
132 #define COLOR_OUTPUT_MODE_I16					0x00000006
133 #define VARYING_NUM_COMPONENTS_VAR0__MASK			0x00000007
134 #define VARYING_NUM_COMPONENTS_VAR0__SHIFT			0
135 #define VARYING_NUM_COMPONENTS_VAR0(x)				(((x) << VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VARYING_NUM_COMPONENTS_VAR0__MASK)
136 #define VARYING_NUM_COMPONENTS_VAR1__MASK			0x00000070
137 #define VARYING_NUM_COMPONENTS_VAR1__SHIFT			4
138 #define VARYING_NUM_COMPONENTS_VAR1(x)				(((x) << VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VARYING_NUM_COMPONENTS_VAR1__MASK)
139 #define VARYING_NUM_COMPONENTS_VAR2__MASK			0x00000700
140 #define VARYING_NUM_COMPONENTS_VAR2__SHIFT			8
141 #define VARYING_NUM_COMPONENTS_VAR2(x)				(((x) << VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VARYING_NUM_COMPONENTS_VAR2__MASK)
142 #define VARYING_NUM_COMPONENTS_VAR3__MASK			0x00007000
143 #define VARYING_NUM_COMPONENTS_VAR3__SHIFT			12
144 #define VARYING_NUM_COMPONENTS_VAR3(x)				(((x) << VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VARYING_NUM_COMPONENTS_VAR3__MASK)
145 #define VARYING_NUM_COMPONENTS_VAR4__MASK			0x00070000
146 #define VARYING_NUM_COMPONENTS_VAR4__SHIFT			16
147 #define VARYING_NUM_COMPONENTS_VAR4(x)				(((x) << VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VARYING_NUM_COMPONENTS_VAR4__MASK)
148 #define VARYING_NUM_COMPONENTS_VAR5__MASK			0x00700000
149 #define VARYING_NUM_COMPONENTS_VAR5__SHIFT			20
150 #define VARYING_NUM_COMPONENTS_VAR5(x)				(((x) << VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VARYING_NUM_COMPONENTS_VAR5__MASK)
151 #define VARYING_NUM_COMPONENTS_VAR6__MASK			0x07000000
152 #define VARYING_NUM_COMPONENTS_VAR6__SHIFT			24
153 #define VARYING_NUM_COMPONENTS_VAR6(x)				(((x) << VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VARYING_NUM_COMPONENTS_VAR6__MASK)
154 #define VARYING_NUM_COMPONENTS_VAR7__MASK			0x70000000
155 #define VARYING_NUM_COMPONENTS_VAR7__SHIFT			28
156 #define VARYING_NUM_COMPONENTS_VAR7(x)				(((x) << VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VARYING_NUM_COMPONENTS_VAR7__MASK)
157 #define VIVS_VS							0x00000000
158 
159 #define VIVS_VS_END_PC						0x00000800
160 
161 #define VIVS_VS_OUTPUT_COUNT					0x00000804
162 
163 #define VIVS_VS_INPUT_COUNT					0x00000808
164 #define VIVS_VS_INPUT_COUNT_COUNT__MASK				0x0000000f
165 #define VIVS_VS_INPUT_COUNT_COUNT__SHIFT			0
166 #define VIVS_VS_INPUT_COUNT_COUNT(x)				(((x) << VIVS_VS_INPUT_COUNT_COUNT__SHIFT) & VIVS_VS_INPUT_COUNT_COUNT__MASK)
167 #define VIVS_VS_INPUT_COUNT_UNK8__MASK				0x00001f00
168 #define VIVS_VS_INPUT_COUNT_UNK8__SHIFT				8
169 #define VIVS_VS_INPUT_COUNT_UNK8(x)				(((x) << VIVS_VS_INPUT_COUNT_UNK8__SHIFT) & VIVS_VS_INPUT_COUNT_UNK8__MASK)
170 #define VIVS_VS_INPUT_COUNT_ID_ENABLE				0x80000000
171 
172 #define VIVS_VS_TEMP_REGISTER_CONTROL				0x0000080c
173 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK		0x0000003f
174 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT		0
175 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		(((x) << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK)
176 
177 #define VIVS_VS_OUTPUT(i0)				       (0x00000810 + 0x4*(i0))
178 #define VIVS_VS_OUTPUT__ESIZE					0x00000004
179 #define VIVS_VS_OUTPUT__LEN					0x00000004
180 #define VIVS_VS_OUTPUT_O0__MASK					0x000000ff
181 #define VIVS_VS_OUTPUT_O0__SHIFT				0
182 #define VIVS_VS_OUTPUT_O0(x)					(((x) << VIVS_VS_OUTPUT_O0__SHIFT) & VIVS_VS_OUTPUT_O0__MASK)
183 #define VIVS_VS_OUTPUT_O1__MASK					0x0000ff00
184 #define VIVS_VS_OUTPUT_O1__SHIFT				8
185 #define VIVS_VS_OUTPUT_O1(x)					(((x) << VIVS_VS_OUTPUT_O1__SHIFT) & VIVS_VS_OUTPUT_O1__MASK)
186 #define VIVS_VS_OUTPUT_O2__MASK					0x00ff0000
187 #define VIVS_VS_OUTPUT_O2__SHIFT				16
188 #define VIVS_VS_OUTPUT_O2(x)					(((x) << VIVS_VS_OUTPUT_O2__SHIFT) & VIVS_VS_OUTPUT_O2__MASK)
189 #define VIVS_VS_OUTPUT_O3__MASK					0xff000000
190 #define VIVS_VS_OUTPUT_O3__SHIFT				24
191 #define VIVS_VS_OUTPUT_O3(x)					(((x) << VIVS_VS_OUTPUT_O3__SHIFT) & VIVS_VS_OUTPUT_O3__MASK)
192 
193 #define VIVS_VS_INPUT(i0)				       (0x00000820 + 0x4*(i0))
194 #define VIVS_VS_INPUT__ESIZE					0x00000004
195 #define VIVS_VS_INPUT__LEN					0x00000004
196 #define VIVS_VS_INPUT_I0__MASK					0x000000ff
197 #define VIVS_VS_INPUT_I0__SHIFT					0
198 #define VIVS_VS_INPUT_I0(x)					(((x) << VIVS_VS_INPUT_I0__SHIFT) & VIVS_VS_INPUT_I0__MASK)
199 #define VIVS_VS_INPUT_I1__MASK					0x0000ff00
200 #define VIVS_VS_INPUT_I1__SHIFT					8
201 #define VIVS_VS_INPUT_I1(x)					(((x) << VIVS_VS_INPUT_I1__SHIFT) & VIVS_VS_INPUT_I1__MASK)
202 #define VIVS_VS_INPUT_I2__MASK					0x00ff0000
203 #define VIVS_VS_INPUT_I2__SHIFT					16
204 #define VIVS_VS_INPUT_I2(x)					(((x) << VIVS_VS_INPUT_I2__SHIFT) & VIVS_VS_INPUT_I2__MASK)
205 #define VIVS_VS_INPUT_I3__MASK					0xff000000
206 #define VIVS_VS_INPUT_I3__SHIFT					24
207 #define VIVS_VS_INPUT_I3(x)					(((x) << VIVS_VS_INPUT_I3__SHIFT) & VIVS_VS_INPUT_I3__MASK)
208 
209 #define VIVS_VS_LOAD_BALANCING					0x00000830
210 #define VIVS_VS_LOAD_BALANCING_A__MASK				0x000000ff
211 #define VIVS_VS_LOAD_BALANCING_A__SHIFT				0
212 #define VIVS_VS_LOAD_BALANCING_A(x)				(((x) << VIVS_VS_LOAD_BALANCING_A__SHIFT) & VIVS_VS_LOAD_BALANCING_A__MASK)
213 #define VIVS_VS_LOAD_BALANCING_B__MASK				0x0000ff00
214 #define VIVS_VS_LOAD_BALANCING_B__SHIFT				8
215 #define VIVS_VS_LOAD_BALANCING_B(x)				(((x) << VIVS_VS_LOAD_BALANCING_B__SHIFT) & VIVS_VS_LOAD_BALANCING_B__MASK)
216 #define VIVS_VS_LOAD_BALANCING_C__MASK				0x00ff0000
217 #define VIVS_VS_LOAD_BALANCING_C__SHIFT				16
218 #define VIVS_VS_LOAD_BALANCING_C(x)				(((x) << VIVS_VS_LOAD_BALANCING_C__SHIFT) & VIVS_VS_LOAD_BALANCING_C__MASK)
219 #define VIVS_VS_LOAD_BALANCING_D__MASK				0xff000000
220 #define VIVS_VS_LOAD_BALANCING_D__SHIFT				24
221 #define VIVS_VS_LOAD_BALANCING_D(x)				(((x) << VIVS_VS_LOAD_BALANCING_D__SHIFT) & VIVS_VS_LOAD_BALANCING_D__MASK)
222 
223 #define VIVS_VS_PERF_COUNTER					0x00000834
224 
225 #define VIVS_VS_START_PC					0x00000838
226 
227 #define VIVS_VS_UNK00850					0x00000850
228 
229 #define VIVS_VS_UNK00854					0x00000854
230 
231 #define VIVS_VS_UNK00858					0x00000858
232 
233 #define VIVS_VS_RANGE						0x0000085c
234 #define VIVS_VS_RANGE_LOW__MASK					0x0000ffff
235 #define VIVS_VS_RANGE_LOW__SHIFT				0
236 #define VIVS_VS_RANGE_LOW(x)					(((x) << VIVS_VS_RANGE_LOW__SHIFT) & VIVS_VS_RANGE_LOW__MASK)
237 #define VIVS_VS_RANGE_HIGH__MASK				0xffff0000
238 #define VIVS_VS_RANGE_HIGH__SHIFT				16
239 #define VIVS_VS_RANGE_HIGH(x)					(((x) << VIVS_VS_RANGE_HIGH__SHIFT) & VIVS_VS_RANGE_HIGH__MASK)
240 
241 #define VIVS_VS_UNIFORM_CACHE					0x00000860
242 #define VIVS_VS_UNIFORM_CACHE_FLUSH				0x00000001
243 #define VIVS_VS_UNIFORM_CACHE_PS				0x00000010
244 #define VIVS_VS_UNIFORM_CACHE_RTNE_ROUNDING			0x00001000
245 
246 #define VIVS_VS_UNIFORM_BASE					0x00000864
247 
248 #define VIVS_VS_ICACHE_CONTROL					0x00000868
249 #define VIVS_VS_ICACHE_CONTROL_ENABLE				0x00000001
250 #define VIVS_VS_ICACHE_CONTROL_FLUSH_VS				0x00000010
251 #define VIVS_VS_ICACHE_CONTROL_FLUSH_PS				0x00000020
252 
253 #define VIVS_VS_INST_ADDR					0x0000086c
254 
255 #define VIVS_VS_HALTI5_OUTPUT_COUNT				0x00000870
256 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK			0x000003ff
257 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT		0
258 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT(x)			(((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK)
259 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK			0x0007ff00
260 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT			8
261 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B(x)			(((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK)
262 
263 #define VIVS_VS_NEWRANGE_LOW					0x00000874
264 
265 #define VIVS_VS_HALTI5_UNK00878					0x00000878
266 
267 #define VIVS_VS_HALTI5_UNK00880					0x00000880
268 
269 #define VIVS_VS_HALTI1_UNK00884					0x00000884
270 
271 #define VIVS_VS_ICACHE_PREFETCH					0x0000088c
272 
273 #define VIVS_VS_ICACHE_UNK00890					0x00000890
274 
275 #define VIVS_VS_HALTI5_UNK00898(i0)			       (0x00000898 + 0x4*(i0))
276 #define VIVS_VS_HALTI5_UNK00898__ESIZE				0x00000004
277 #define VIVS_VS_HALTI5_UNK00898__LEN				0x00000002
278 
279 #define VIVS_VS_HALTI5_UNK008A0					0x000008a0
280 #define VIVS_VS_HALTI5_UNK008A0_A__MASK				0x0000003f
281 #define VIVS_VS_HALTI5_UNK008A0_A__SHIFT			0
282 #define VIVS_VS_HALTI5_UNK008A0_A(x)				(((x) << VIVS_VS_HALTI5_UNK008A0_A__SHIFT) & VIVS_VS_HALTI5_UNK008A0_A__MASK)
283 #define VIVS_VS_HALTI5_UNK008A0_B__MASK				0x0007f000
284 #define VIVS_VS_HALTI5_UNK008A0_B__SHIFT			12
285 #define VIVS_VS_HALTI5_UNK008A0_B(x)				(((x) << VIVS_VS_HALTI5_UNK008A0_B__SHIFT) & VIVS_VS_HALTI5_UNK008A0_B__MASK)
286 #define VIVS_VS_HALTI5_UNK008A0_C__MASK				0x1ff00000
287 #define VIVS_VS_HALTI5_UNK008A0_C__SHIFT			20
288 #define VIVS_VS_HALTI5_UNK008A0_C(x)				(((x) << VIVS_VS_HALTI5_UNK008A0_C__SHIFT) & VIVS_VS_HALTI5_UNK008A0_C__MASK)
289 
290 #define VIVS_VS_SAMPLER_BASE					0x000008a8
291 
292 #define VIVS_VS_ICACHE_INVALIDATE				0x000008b0
293 #define VIVS_VS_ICACHE_INVALIDATE_UNK0				0x00000001
294 #define VIVS_VS_ICACHE_INVALIDATE_UNK1				0x00000002
295 #define VIVS_VS_ICACHE_INVALIDATE_UNK2				0x00000004
296 #define VIVS_VS_ICACHE_INVALIDATE_UNK3				0x00000008
297 #define VIVS_VS_ICACHE_INVALIDATE_UNK4				0x00000010
298 
299 #define VIVS_VS_HALTI5_UNK008B8					0x000008b8
300 
301 #define VIVS_VS_NEWRANGE_HIGH					0x000008bc
302 
303 #define VIVS_VS_HALTI5_INPUT(i0)			       (0x000008c0 + 0x4*(i0))
304 #define VIVS_VS_HALTI5_INPUT__ESIZE				0x00000004
305 #define VIVS_VS_HALTI5_INPUT__LEN				0x00000008
306 #define VIVS_VS_HALTI5_INPUT_I0__MASK				0x000000ff
307 #define VIVS_VS_HALTI5_INPUT_I0__SHIFT				0
308 #define VIVS_VS_HALTI5_INPUT_I0(x)				(((x) << VIVS_VS_HALTI5_INPUT_I0__SHIFT) & VIVS_VS_HALTI5_INPUT_I0__MASK)
309 #define VIVS_VS_HALTI5_INPUT_I1__MASK				0x0000ff00
310 #define VIVS_VS_HALTI5_INPUT_I1__SHIFT				8
311 #define VIVS_VS_HALTI5_INPUT_I1(x)				(((x) << VIVS_VS_HALTI5_INPUT_I1__SHIFT) & VIVS_VS_HALTI5_INPUT_I1__MASK)
312 #define VIVS_VS_HALTI5_INPUT_I2__MASK				0x00ff0000
313 #define VIVS_VS_HALTI5_INPUT_I2__SHIFT				16
314 #define VIVS_VS_HALTI5_INPUT_I2(x)				(((x) << VIVS_VS_HALTI5_INPUT_I2__SHIFT) & VIVS_VS_HALTI5_INPUT_I2__MASK)
315 #define VIVS_VS_HALTI5_INPUT_I3__MASK				0xff000000
316 #define VIVS_VS_HALTI5_INPUT_I3__SHIFT				24
317 #define VIVS_VS_HALTI5_INPUT_I3(x)				(((x) << VIVS_VS_HALTI5_INPUT_I3__SHIFT) & VIVS_VS_HALTI5_INPUT_I3__MASK)
318 
319 #define VIVS_VS_HALTI5_OUTPUT(i0)			       (0x000008e0 + 0x4*(i0))
320 #define VIVS_VS_HALTI5_OUTPUT__ESIZE				0x00000004
321 #define VIVS_VS_HALTI5_OUTPUT__LEN				0x00000008
322 #define VIVS_VS_HALTI5_OUTPUT_O0__MASK				0x000000ff
323 #define VIVS_VS_HALTI5_OUTPUT_O0__SHIFT				0
324 #define VIVS_VS_HALTI5_OUTPUT_O0(x)				(((x) << VIVS_VS_HALTI5_OUTPUT_O0__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O0__MASK)
325 #define VIVS_VS_HALTI5_OUTPUT_O1__MASK				0x0000ff00
326 #define VIVS_VS_HALTI5_OUTPUT_O1__SHIFT				8
327 #define VIVS_VS_HALTI5_OUTPUT_O1(x)				(((x) << VIVS_VS_HALTI5_OUTPUT_O1__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O1__MASK)
328 #define VIVS_VS_HALTI5_OUTPUT_O2__MASK				0x00ff0000
329 #define VIVS_VS_HALTI5_OUTPUT_O2__SHIFT				16
330 #define VIVS_VS_HALTI5_OUTPUT_O2(x)				(((x) << VIVS_VS_HALTI5_OUTPUT_O2__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O2__MASK)
331 #define VIVS_VS_HALTI5_OUTPUT_O3__MASK				0xff000000
332 #define VIVS_VS_HALTI5_OUTPUT_O3__SHIFT				24
333 #define VIVS_VS_HALTI5_OUTPUT_O3(x)				(((x) << VIVS_VS_HALTI5_OUTPUT_O3__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O3__MASK)
334 
335 #define VIVS_VS_INST_MEM(i0)				       (0x00004000 + 0x4*(i0))
336 #define VIVS_VS_INST_MEM__ESIZE					0x00000004
337 #define VIVS_VS_INST_MEM__LEN					0x00000400
338 
339 #define VIVS_VS_UNIFORMS(i0)				       (0x00005000 + 0x4*(i0))
340 #define VIVS_VS_UNIFORMS__ESIZE					0x00000004
341 #define VIVS_VS_UNIFORMS__LEN					0x00000400
342 
343 #define VIVS_VS_ICACHE_COUNT					0x00015604
344 
345 #define VIVS_CL							0x00000000
346 
347 #define VIVS_CL_CONFIG						0x00000900
348 #define VIVS_CL_CONFIG_DIMENSIONS__MASK				0x00000003
349 #define VIVS_CL_CONFIG_DIMENSIONS__SHIFT			0
350 #define VIVS_CL_CONFIG_DIMENSIONS(x)				(((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK)
351 #define VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK			0x00000070
352 #define VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT			4
353 #define VIVS_CL_CONFIG_TRAVERSE_ORDER(x)			(((x) << VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT) & VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK)
354 #define VIVS_CL_CONFIG_ENABLE_SWATH_X				0x00000100
355 #define VIVS_CL_CONFIG_ENABLE_SWATH_Y				0x00000200
356 #define VIVS_CL_CONFIG_ENABLE_SWATH_Z				0x00000400
357 #define VIVS_CL_CONFIG_SWATH_SIZE_X__MASK			0x0000f000
358 #define VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT			12
359 #define VIVS_CL_CONFIG_SWATH_SIZE_X(x)				(((x) << VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_X__MASK)
360 #define VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK			0x000f0000
361 #define VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT			16
362 #define VIVS_CL_CONFIG_SWATH_SIZE_Y(x)				(((x) << VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK)
363 #define VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK			0x00f00000
364 #define VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT			20
365 #define VIVS_CL_CONFIG_SWATH_SIZE_Z(x)				(((x) << VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK)
366 #define VIVS_CL_CONFIG_VALUE_ORDER__MASK			0x07000000
367 #define VIVS_CL_CONFIG_VALUE_ORDER__SHIFT			24
368 #define VIVS_CL_CONFIG_VALUE_ORDER(x)				(((x) << VIVS_CL_CONFIG_VALUE_ORDER__SHIFT) & VIVS_CL_CONFIG_VALUE_ORDER__MASK)
369 
370 #define VIVS_CL_GLOBAL_X					0x00000904
371 #define VIVS_CL_GLOBAL_X_SIZE__MASK				0x0000ffff
372 #define VIVS_CL_GLOBAL_X_SIZE__SHIFT				0
373 #define VIVS_CL_GLOBAL_X_SIZE(x)				(((x) << VIVS_CL_GLOBAL_X_SIZE__SHIFT) & VIVS_CL_GLOBAL_X_SIZE__MASK)
374 #define VIVS_CL_GLOBAL_X_OFFSET__MASK				0xffff0000
375 #define VIVS_CL_GLOBAL_X_OFFSET__SHIFT				16
376 #define VIVS_CL_GLOBAL_X_OFFSET(x)				(((x) << VIVS_CL_GLOBAL_X_OFFSET__SHIFT) & VIVS_CL_GLOBAL_X_OFFSET__MASK)
377 
378 #define VIVS_CL_GLOBAL_Y					0x00000908
379 #define VIVS_CL_GLOBAL_Y_SIZE__MASK				0x0000ffff
380 #define VIVS_CL_GLOBAL_Y_SIZE__SHIFT				0
381 #define VIVS_CL_GLOBAL_Y_SIZE(x)				(((x) << VIVS_CL_GLOBAL_Y_SIZE__SHIFT) & VIVS_CL_GLOBAL_Y_SIZE__MASK)
382 #define VIVS_CL_GLOBAL_Y_OFFSET__MASK				0xffff0000
383 #define VIVS_CL_GLOBAL_Y_OFFSET__SHIFT				16
384 #define VIVS_CL_GLOBAL_Y_OFFSET(x)				(((x) << VIVS_CL_GLOBAL_Y_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Y_OFFSET__MASK)
385 
386 #define VIVS_CL_GLOBAL_Z					0x0000090c
387 #define VIVS_CL_GLOBAL_Z_SIZE__MASK				0x0000ffff
388 #define VIVS_CL_GLOBAL_Z_SIZE__SHIFT				0
389 #define VIVS_CL_GLOBAL_Z_SIZE(x)				(((x) << VIVS_CL_GLOBAL_Z_SIZE__SHIFT) & VIVS_CL_GLOBAL_Z_SIZE__MASK)
390 #define VIVS_CL_GLOBAL_Z_OFFSET__MASK				0xffff0000
391 #define VIVS_CL_GLOBAL_Z_OFFSET__SHIFT				16
392 #define VIVS_CL_GLOBAL_Z_OFFSET(x)				(((x) << VIVS_CL_GLOBAL_Z_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Z_OFFSET__MASK)
393 
394 #define VIVS_CL_WORKGROUP_X					0x00000910
395 #define VIVS_CL_WORKGROUP_X_SIZE__MASK				0x000003ff
396 #define VIVS_CL_WORKGROUP_X_SIZE__SHIFT				0
397 #define VIVS_CL_WORKGROUP_X_SIZE(x)				(((x) << VIVS_CL_WORKGROUP_X_SIZE__SHIFT) & VIVS_CL_WORKGROUP_X_SIZE__MASK)
398 #define VIVS_CL_WORKGROUP_X_COUNT__MASK				0xffff0000
399 #define VIVS_CL_WORKGROUP_X_COUNT__SHIFT			16
400 #define VIVS_CL_WORKGROUP_X_COUNT(x)				(((x) << VIVS_CL_WORKGROUP_X_COUNT__SHIFT) & VIVS_CL_WORKGROUP_X_COUNT__MASK)
401 
402 #define VIVS_CL_WORKGROUP_Y					0x00000914
403 #define VIVS_CL_WORKGROUP_Y_SIZE__MASK				0x000003ff
404 #define VIVS_CL_WORKGROUP_Y_SIZE__SHIFT				0
405 #define VIVS_CL_WORKGROUP_Y_SIZE(x)				(((x) << VIVS_CL_WORKGROUP_Y_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Y_SIZE__MASK)
406 #define VIVS_CL_WORKGROUP_Y_COUNT__MASK				0xffff0000
407 #define VIVS_CL_WORKGROUP_Y_COUNT__SHIFT			16
408 #define VIVS_CL_WORKGROUP_Y_COUNT(x)				(((x) << VIVS_CL_WORKGROUP_Y_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Y_COUNT__MASK)
409 
410 #define VIVS_CL_WORKGROUP_Z					0x00000918
411 #define VIVS_CL_WORKGROUP_Z_SIZE__MASK				0x000003ff
412 #define VIVS_CL_WORKGROUP_Z_SIZE__SHIFT				0
413 #define VIVS_CL_WORKGROUP_Z_SIZE(x)				(((x) << VIVS_CL_WORKGROUP_Z_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Z_SIZE__MASK)
414 #define VIVS_CL_WORKGROUP_Z_COUNT__MASK				0xffff0000
415 #define VIVS_CL_WORKGROUP_Z_COUNT__SHIFT			16
416 #define VIVS_CL_WORKGROUP_Z_COUNT(x)				(((x) << VIVS_CL_WORKGROUP_Z_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Z_COUNT__MASK)
417 
418 #define VIVS_CL_THREAD_ALLOCATION				0x0000091c
419 
420 #define VIVS_CL_KICKER						0x00000920
421 
422 #define VIVS_CL_UNK00924					0x00000924
423 
424 #define VIVS_CL_UNK00940					0x00000940
425 
426 #define VIVS_CL_UNK00944					0x00000944
427 
428 #define VIVS_CL_UNK00948					0x00000948
429 
430 #define VIVS_CL_UNK0094C					0x0000094c
431 
432 #define VIVS_CL_UNK00950					0x00000950
433 
434 #define VIVS_CL_UNK00954					0x00000954
435 
436 #define VIVS_CL_HALTI5_UNK00958					0x00000958
437 
438 #define VIVS_CL_HALTI5_UNK0095C					0x0000095c
439 
440 #define VIVS_CL_HALTI5_UNK00960					0x00000960
441 
442 #define VIVS_PA							0x00000000
443 
444 #define VIVS_PA_VIEWPORT_SCALE_X				0x00000a00
445 
446 #define VIVS_PA_VIEWPORT_SCALE_Y				0x00000a04
447 
448 #define VIVS_PA_VIEWPORT_SCALE_Z				0x00000a08
449 
450 #define VIVS_PA_VIEWPORT_OFFSET_X				0x00000a0c
451 
452 #define VIVS_PA_VIEWPORT_OFFSET_Y				0x00000a10
453 
454 #define VIVS_PA_VIEWPORT_OFFSET_Z				0x00000a14
455 
456 #define VIVS_PA_LINE_WIDTH					0x00000a18
457 
458 #define VIVS_PA_POINT_SIZE					0x00000a1c
459 
460 #define VIVS_PA_UNK00A24					0x00000a24
461 
462 #define VIVS_PA_SYSTEM_MODE					0x00000a28
463 #define VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST		0x00000001
464 #define VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER			0x00000010
465 
466 #define VIVS_PA_W_CLIP_LIMIT					0x00000a2c
467 
468 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT				0x00000a30
469 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK		0x000000ff
470 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT		0
471 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0(x)			(((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK)
472 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK		0x0000ff00
473 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT		8
474 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT(x)		(((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK)
475 
476 #define VIVS_PA_CONFIG						0x00000a34
477 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE			0x00000004
478 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE_MASK			0x00000008
479 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE			0x00000010
480 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE_MASK			0x00000020
481 #define VIVS_PA_CONFIG_CULL_FACE_MODE__MASK			0x00000300
482 #define VIVS_PA_CONFIG_CULL_FACE_MODE__SHIFT			8
483 #define VIVS_PA_CONFIG_CULL_FACE_MODE_OFF			0x00000000
484 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CW			0x00000100
485 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CCW			0x00000200
486 #define VIVS_PA_CONFIG_CULL_FACE_MODE_MASK			0x00000400
487 #define VIVS_PA_CONFIG_FILL_MODE__MASK				0x00003000
488 #define VIVS_PA_CONFIG_FILL_MODE__SHIFT				12
489 #define VIVS_PA_CONFIG_FILL_MODE_POINT				0x00000000
490 #define VIVS_PA_CONFIG_FILL_MODE_WIREFRAME			0x00001000
491 #define VIVS_PA_CONFIG_FILL_MODE_SOLID				0x00002000
492 #define VIVS_PA_CONFIG_FILL_MODE_MASK				0x00004000
493 #define VIVS_PA_CONFIG_SHADE_MODEL__MASK			0x00030000
494 #define VIVS_PA_CONFIG_SHADE_MODEL__SHIFT			16
495 #define VIVS_PA_CONFIG_SHADE_MODEL_FLAT				0x00000000
496 #define VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH			0x00010000
497 #define VIVS_PA_CONFIG_SHADE_MODEL_MASK				0x00040000
498 #define VIVS_PA_CONFIG_WIDE_LINE				0x00400000
499 #define VIVS_PA_CONFIG_WIDE_LINE_MASK				0x00800000
500 
501 #define VIVS_PA_WIDE_LINE_WIDTH0				0x00000a38
502 
503 #define VIVS_PA_WIDE_LINE_WIDTH1				0x00000a3c
504 
505 #define VIVS_PA_SHADER_ATTRIBUTES(i0)			       (0x00000a40 + 0x4*(i0))
506 #define VIVS_PA_SHADER_ATTRIBUTES__ESIZE			0x00000004
507 #define VIVS_PA_SHADER_ATTRIBUTES__LEN				0x0000000a
508 #define VIVS_PA_SHADER_ATTRIBUTES_BYPASS_FLAT			0x00000001
509 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK			0x000000f0
510 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT			4
511 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4(x)			(((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK)
512 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK			0x00000f00
513 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT			8
514 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8(x)			(((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK)
515 
516 #define VIVS_PA_VIEWPORT_UNK00A80				0x00000a80
517 
518 #define VIVS_PA_VIEWPORT_UNK00A84				0x00000a84
519 
520 #define VIVS_PA_FLAGS						0x00000a88
521 #define VIVS_PA_FLAGS_UNK24					0x01000000
522 #define VIVS_PA_FLAGS_ZCONVERT_BYPASS				0x40000000
523 
524 #define VIVS_PA_ZFARCLIPPING					0x00000a8c
525 
526 #define VIVS_PA_VARYING_NUM_COMPONENTS(i0)		       (0x00000a90 + 0x4*(i0))
527 #define VIVS_PA_VARYING_NUM_COMPONENTS__ESIZE			0x00000004
528 #define VIVS_PA_VARYING_NUM_COMPONENTS__LEN			0x00000004
529 
530 #define VIVS_PA_VS_OUTPUT_COUNT					0x00000aa8
531 
532 #define VIVS_SE							0x00000000
533 
534 #define VIVS_SE_SCISSOR_LEFT					0x00000c00
535 
536 #define VIVS_SE_SCISSOR_TOP					0x00000c04
537 
538 #define VIVS_SE_SCISSOR_RIGHT					0x00000c08
539 
540 #define VIVS_SE_SCISSOR_BOTTOM					0x00000c0c
541 
542 #define VIVS_SE_DEPTH_SCALE					0x00000c10
543 
544 #define VIVS_SE_DEPTH_BIAS					0x00000c14
545 
546 #define VIVS_SE_CONFIG						0x00000c18
547 #define VIVS_SE_CONFIG_LAST_PIXEL_ENABLE			0x00000001
548 
549 #define VIVS_SE_UNK00C1C					0x00000c1c
550 
551 #define VIVS_SE_CLIP_RIGHT					0x00000c20
552 
553 #define VIVS_SE_CLIP_BOTTOM					0x00000c24
554 
555 #define VIVS_RA							0x00000000
556 
557 #define VIVS_RA_CONTROL						0x00000e00
558 #define VIVS_RA_CONTROL_UNK0					0x00000001
559 #define VIVS_RA_CONTROL_LAST_VARYING_2X				0x00000002
560 
561 #define VIVS_RA_MULTISAMPLE_UNK00E04				0x00000e04
562 
563 #define VIVS_RA_EARLY_DEPTH					0x00000e08
564 #define VIVS_RA_EARLY_DEPTH_TEST_ENABLE				0x00000001
565 #define VIVS_RA_EARLY_DEPTH_HDEPTH_DISABLE			0x01000000
566 #define VIVS_RA_EARLY_DEPTH_WRITE_DISABLE			0x10000000
567 
568 #define VIVS_RA_UNK00E0C					0x00000e0c
569 
570 #define VIVS_RA_MULTISAMPLE_UNK00E10(i0)		       (0x00000e10 + 0x4*(i0))
571 #define VIVS_RA_MULTISAMPLE_UNK00E10__ESIZE			0x00000004
572 #define VIVS_RA_MULTISAMPLE_UNK00E10__LEN			0x00000004
573 
574 #define VIVS_RA_HDEPTH_CONTROL					0x00000e20
575 #define VIVS_RA_HDEPTH_CONTROL_UNK0				0x00000001
576 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK			0x00007000
577 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT			12
578 #define VIVS_RA_HDEPTH_CONTROL_COMPARE(x)			(((x) << VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT) & VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK)
579 
580 #define VIVS_RA_UNK00E24					0x00000e24
581 
582 #define VIVS_RA_HALTI5_UNK00E34					0x00000e34
583 
584 #define VIVS_RA_CENTROID_TABLE(i0)			       (0x00000e40 + 0x4*(i0))
585 #define VIVS_RA_CENTROID_TABLE__ESIZE				0x00000004
586 #define VIVS_RA_CENTROID_TABLE__LEN				0x00000010
587 
588 #define VIVS_PS							0x00000000
589 
590 #define VIVS_PS_END_PC						0x00001000
591 
592 #define VIVS_PS_OUTPUT_REG					0x00001004
593 
594 #define VIVS_PS_INPUT_COUNT					0x00001008
595 #define VIVS_PS_INPUT_COUNT_COUNT__MASK				0x0000000f
596 #define VIVS_PS_INPUT_COUNT_COUNT__SHIFT			0
597 #define VIVS_PS_INPUT_COUNT_COUNT(x)				(((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK)
598 #define VIVS_PS_INPUT_COUNT_UNK8__MASK				0x00001f00
599 #define VIVS_PS_INPUT_COUNT_UNK8__SHIFT				8
600 #define VIVS_PS_INPUT_COUNT_UNK8(x)				(((x) << VIVS_PS_INPUT_COUNT_UNK8__SHIFT) & VIVS_PS_INPUT_COUNT_UNK8__MASK)
601 #define VIVS_PS_INPUT_COUNT_DUAL16				0x00010000
602 
603 #define VIVS_PS_TEMP_REGISTER_CONTROL				0x0000100c
604 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK		0x0000003f
605 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT		0
606 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		(((x) << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK)
607 
608 #define VIVS_PS_CONTROL						0x00001010
609 #define VIVS_PS_CONTROL_BYPASS					0x00000001
610 #define VIVS_PS_CONTROL_SATURATE_RT0				0x00000002
611 #define VIVS_PS_CONTROL_SATURATE_RT1				0x00000004
612 #define VIVS_PS_CONTROL_SATURATE_RT2				0x00000008
613 #define VIVS_PS_CONTROL_SATURATE_RT3				0x00000010
614 #define VIVS_PS_CONTROL_RT_COUNT__MASK				0x00000700
615 #define VIVS_PS_CONTROL_RT_COUNT__SHIFT				8
616 #define VIVS_PS_CONTROL_RT_COUNT(x)				(((x) << VIVS_PS_CONTROL_RT_COUNT__SHIFT) & VIVS_PS_CONTROL_RT_COUNT__MASK)
617 
618 #define VIVS_PS_PERF_COUNTER					0x00001014
619 
620 #define VIVS_PS_START_PC					0x00001018
621 
622 #define VIVS_PS_RANGE						0x0000101c
623 #define VIVS_PS_RANGE_LOW__MASK					0x0000ffff
624 #define VIVS_PS_RANGE_LOW__SHIFT				0
625 #define VIVS_PS_RANGE_LOW(x)					(((x) << VIVS_PS_RANGE_LOW__SHIFT) & VIVS_PS_RANGE_LOW__MASK)
626 #define VIVS_PS_RANGE_HIGH__MASK				0xffff0000
627 #define VIVS_PS_RANGE_HIGH__SHIFT				16
628 #define VIVS_PS_RANGE_HIGH(x)					(((x) << VIVS_PS_RANGE_HIGH__SHIFT) & VIVS_PS_RANGE_HIGH__MASK)
629 
630 #define VIVS_PS_UNIFORM_BASE					0x00001024
631 
632 #define VIVS_PS_INST_ADDR					0x00001028
633 
634 #define VIVS_PS_CONTROL2					0x0000102c
635 #define VIVS_PS_CONTROL2_SATURATE_RT4				0x00000080
636 #define VIVS_PS_CONTROL2_SATURATE_RT5				0x00008000
637 #define VIVS_PS_CONTROL2_SATURATE_RT6				0x00800000
638 #define VIVS_PS_CONTROL2_SATURATE_RT7				0x80000000
639 
640 #define VIVS_PS_CONTROL_EXT					0x00001030
641 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK			0x00000007
642 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT			0
643 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(x)			(((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK)
644 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK			0x00000070
645 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT			4
646 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1(x)			(((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK)
647 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK			0x00000700
648 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT			8
649 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2(x)			(((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK)
650 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK			0x00007000
651 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT			12
652 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3(x)			(((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK)
653 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK			0x00070000
654 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT			16
655 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4(x)			(((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK)
656 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK			0x00700000
657 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT			20
658 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5(x)			(((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK)
659 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK			0x07000000
660 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT			24
661 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6(x)			(((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK)
662 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK			0x70000000
663 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT			28
664 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7(x)			(((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK)
665 
666 #define VIVS_PS_UNK01034					0x00001034
667 
668 #define VIVS_PS_UNK01038					0x00001038
669 
670 #define VIVS_PS_HALTI3_UNK0103C					0x0000103c
671 
672 #define VIVS_PS_UNK01040(i0)				       (0x00001040 + 0x4*(i0))
673 #define VIVS_PS_UNK01040__ESIZE					0x00000004
674 #define VIVS_PS_UNK01040__LEN					0x00000002
675 
676 #define VIVS_PS_ICACHE_PREFETCH					0x00001048
677 
678 #define VIVS_PS_ICACHE_UNK0104C					0x0000104c
679 
680 #define VIVS_PS_MSAA_CONFIG					0x00001054
681 
682 #define VIVS_PS_SAMPLER_BASE					0x00001058
683 
684 #define VIVS_PS_VARYING_NUM_COMPONENTS(i0)		       (0x00001080 + 0x4*(i0))
685 #define VIVS_PS_VARYING_NUM_COMPONENTS__ESIZE			0x00000004
686 #define VIVS_PS_VARYING_NUM_COMPONENTS__LEN			0x00000004
687 
688 #define VIVS_PS_NEWRANGE_LOW					0x0000087c
689 
690 #define VIVS_PS_NEWRANGE_HIGH					0x00001090
691 
692 #define VIVS_PS_ICACHE_COUNT					0x00001094
693 
694 #define VIVS_PS_HALTI5_UNK01098					0x00001098
695 
696 #define VIVS_PS_INST_MEM(i0)				       (0x00006000 + 0x4*(i0))
697 #define VIVS_PS_INST_MEM__ESIZE					0x00000004
698 #define VIVS_PS_INST_MEM__LEN					0x00000400
699 
700 #define VIVS_PS_UNIFORMS(i0)				       (0x00007000 + 0x4*(i0))
701 #define VIVS_PS_UNIFORMS__ESIZE					0x00000004
702 #define VIVS_PS_UNIFORMS__LEN					0x00000400
703 
704 #define VIVS_GS							0x00000000
705 
706 #define VIVS_GS_UNK01100					0x00001100
707 
708 #define VIVS_GS_UNK01104					0x00001104
709 
710 #define VIVS_GS_UNK01108					0x00001108
711 
712 #define VIVS_GS_UNK0110C					0x0000110c
713 
714 #define VIVS_GS_UNK01110					0x00001110
715 
716 #define VIVS_GS_UNK01114					0x00001114
717 
718 #define VIVS_GS_ICACHE_PREFETCH					0x00001118
719 
720 #define VIVS_GS_UNK0111C					0x0000111c
721 
722 #define VIVS_GS_UNK01120(i0)				       (0x00001120 + 0x4*(i0))
723 #define VIVS_GS_UNK01120__ESIZE					0x00000004
724 #define VIVS_GS_UNK01120__LEN					0x00000008
725 
726 #define VIVS_GS_UNK01140					0x00001140
727 
728 #define VIVS_GS_UNK01144					0x00001144
729 
730 #define VIVS_GS_UNK01148					0x00001148
731 
732 #define VIVS_GS_UNK0114C					0x0000114c
733 
734 #define VIVS_GS_UNK01154					0x00001154
735 
736 #define VIVS_TCS						0x00000000
737 
738 #define VIVS_TCS_UNK007C0					0x000007c0
739 
740 #define VIVS_TCS_UNK14A00					0x00014a00
741 
742 #define VIVS_TCS_UNK14A04					0x00014a04
743 
744 #define VIVS_TCS_UNK14A08					0x00014a08
745 
746 #define VIVS_TCS_ICACHE_PREFETCH				0x00014a0c
747 
748 #define VIVS_TCS_UNK14A10					0x00014a10
749 
750 #define VIVS_TCS_UNK14A14					0x00014a14
751 
752 #define VIVS_TCS_UNK14A18					0x00014a18
753 
754 #define VIVS_TCS_UNK14A1C					0x00014a1c
755 
756 #define VIVS_TCS_UNK14A20(i0)				       (0x00014a20 + 0x4*(i0))
757 #define VIVS_TCS_UNK14A20__ESIZE				0x00000004
758 #define VIVS_TCS_UNK14A20__LEN					0x00000008
759 
760 #define VIVS_TCS_UNK14A40					0x00014a40
761 
762 #define VIVS_TCS_UNK14A44					0x00014a44
763 
764 #define VIVS_TCS_UNK14A4C					0x00014a4c
765 
766 #define VIVS_TES						0x00000000
767 
768 #define VIVS_TES_UNK14B00					0x00014b00
769 
770 #define VIVS_TES_UNK14B04					0x00014b04
771 
772 #define VIVS_TES_UNK14B08					0x00014b08
773 
774 #define VIVS_TES_UNK14B0C					0x00014b0c
775 
776 #define VIVS_TES_ICACHE_PREFETCH				0x00014b10
777 
778 #define VIVS_TES_UNK14B14					0x00014b14
779 
780 #define VIVS_TES_UNK14B18					0x00014b18
781 
782 #define VIVS_TES_UNK14B1C					0x00014b1c
783 
784 #define VIVS_TES_UNK14B20					0x00014b20
785 
786 #define VIVS_TES_UNK14B24					0x00014b24
787 
788 #define VIVS_TES_UNK14B2C					0x00014b2c
789 
790 #define VIVS_TES_UNK14B34					0x00014b34
791 
792 #define VIVS_TES_UNK14B40(i0)				       (0x00014b40 + 0x4*(i0))
793 #define VIVS_TES_UNK14B40__ESIZE				0x00000004
794 #define VIVS_TES_UNK14B40__LEN					0x00000008
795 
796 #define VIVS_TFB						0x00000000
797 
798 #define VIVS_TFB_UNK1C000					0x0001c000
799 
800 #define VIVS_TFB_UNK1C008					0x0001c008
801 
802 #define VIVS_TFB_FLUSH						0x0001c00c
803 
804 #define VIVS_TFB_UNK1C014					0x0001c014
805 
806 #define VIVS_TFB_UNK1C040(i0)				       (0x0001c040 + 0x4*(i0))
807 #define VIVS_TFB_UNK1C040__ESIZE				0x00000004
808 #define VIVS_TFB_UNK1C040__LEN					0x00000004
809 
810 #define VIVS_TFB_UNK1C080(i0)				       (0x0001c080 + 0x4*(i0))
811 #define VIVS_TFB_UNK1C080__ESIZE				0x00000004
812 #define VIVS_TFB_UNK1C080__LEN					0x00000004
813 
814 #define VIVS_TFB_UNK1C0C0(i0)				       (0x0001c0c0 + 0x4*(i0))
815 #define VIVS_TFB_UNK1C0C0__ESIZE				0x00000004
816 #define VIVS_TFB_UNK1C0C0__LEN					0x00000004
817 
818 #define VIVS_TFB_UNK1C100(i0)				       (0x0001c100 + 0x4*(i0))
819 #define VIVS_TFB_UNK1C100__ESIZE				0x00000004
820 #define VIVS_TFB_UNK1C100__LEN					0x00000004
821 
822 #define VIVS_TFB_UNK1C800(i0)				       (0x0001c800 + 0x4*(i0))
823 #define VIVS_TFB_UNK1C800__ESIZE				0x00000004
824 #define VIVS_TFB_UNK1C800__LEN					0x00000200
825 
826 #define VIVS_PE							0x00000000
827 
828 #define VIVS_PE_DEPTH_CONFIG					0x00001400
829 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__MASK			0x00000003
830 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__SHIFT			0
831 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE			0x00000000
832 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z			0x00000001
833 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_W			0x00000002
834 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_MASK			0x00000008
835 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__MASK			0x00000010
836 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__SHIFT		4
837 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16			0x00000000
838 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D24S8			0x00000010
839 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_MASK			0x00000020
840 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK			0x00000700
841 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT			8
842 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(x)			(((x) << VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT) & VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK)
843 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC_MASK			0x00000800
844 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE			0x00001000
845 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE_MASK			0x00002000
846 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z				0x00010000
847 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z_MASK			0x00020000
848 #define VIVS_PE_DEPTH_CONFIG_UNK18				0x00040000
849 #define VIVS_PE_DEPTH_CONFIG_UNK18_MASK				0x00080000
850 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH				0x00100000
851 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH_MASK			0x00200000
852 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS				0x01000000
853 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS_MASK			0x02000000
854 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED			0x04000000
855 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED_MASK			0x08000000
856 
857 #define VIVS_PE_DEPTH_NEAR					0x00001404
858 
859 #define VIVS_PE_DEPTH_FAR					0x00001408
860 
861 #define VIVS_PE_DEPTH_NORMALIZE					0x0000140c
862 
863 #define VIVS_PE_DEPTH_ADDR					0x00001410
864 
865 #define VIVS_PE_DEPTH_STRIDE					0x00001414
866 
867 #define VIVS_PE_STENCIL_OP					0x00001418
868 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK			0x00000007
869 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT			0
870 #define VIVS_PE_STENCIL_OP_FUNC_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK)
871 #define VIVS_PE_STENCIL_OP_FUNC_FRONT_MASK			0x00000008
872 #define VIVS_PE_STENCIL_OP_PASS_FRONT__MASK			0x00000070
873 #define VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT			4
874 #define VIVS_PE_STENCIL_OP_PASS_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_PASS_FRONT__MASK)
875 #define VIVS_PE_STENCIL_OP_PASS_FRONT_MASK			0x00000080
876 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK			0x00000700
877 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT			8
878 #define VIVS_PE_STENCIL_OP_FAIL_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK)
879 #define VIVS_PE_STENCIL_OP_FAIL_FRONT_MASK			0x00000800
880 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK		0x00007000
881 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT		12
882 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK)
883 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT_MASK		0x00008000
884 #define VIVS_PE_STENCIL_OP_FUNC_BACK__MASK			0x00070000
885 #define VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT			16
886 #define VIVS_PE_STENCIL_OP_FUNC_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_BACK__MASK)
887 #define VIVS_PE_STENCIL_OP_FUNC_BACK_MASK			0x00080000
888 #define VIVS_PE_STENCIL_OP_PASS_BACK__MASK			0x00700000
889 #define VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT			20
890 #define VIVS_PE_STENCIL_OP_PASS_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT) & VIVS_PE_STENCIL_OP_PASS_BACK__MASK)
891 #define VIVS_PE_STENCIL_OP_PASS_BACK_MASK			0x00800000
892 #define VIVS_PE_STENCIL_OP_FAIL_BACK__MASK			0x07000000
893 #define VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT			24
894 #define VIVS_PE_STENCIL_OP_FAIL_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_BACK__MASK)
895 #define VIVS_PE_STENCIL_OP_FAIL_BACK_MASK			0x08000000
896 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK		0x70000000
897 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT		28
898 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(x)			(((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK)
899 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK_MASK			0x80000000
900 
901 #define VIVS_PE_STENCIL_CONFIG					0x0000141c
902 #define VIVS_PE_STENCIL_CONFIG_MODE__MASK			0x00000003
903 #define VIVS_PE_STENCIL_CONFIG_MODE__SHIFT			0
904 #define VIVS_PE_STENCIL_CONFIG_MODE_DISABLED			0x00000000
905 #define VIVS_PE_STENCIL_CONFIG_MODE_ONE_SIDED			0x00000001
906 #define VIVS_PE_STENCIL_CONFIG_MODE_TWO_SIDED			0x00000002
907 #define VIVS_PE_STENCIL_CONFIG_MODE_MASK			0x00000010
908 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT_MASK			0x00000020
909 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT_MASK			0x00000040
910 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_MASK			0x00000080
911 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK			0x0000ff00
912 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT			8
913 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT(x)			(((x) << VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK)
914 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK			0x00ff0000
915 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT		16
916 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT(x)			(((x) << VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK)
917 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK		0xff000000
918 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT		24
919 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(x)		(((x) << VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK)
920 
921 #define VIVS_PE_ALPHA_OP					0x00001420
922 #define VIVS_PE_ALPHA_OP_ALPHA_TEST				0x00000001
923 #define VIVS_PE_ALPHA_OP_ALPHA_TEST_MASK			0x00000002
924 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK			0x00000070
925 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT			4
926 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC(x)				(((x) << VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK)
927 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC_MASK			0x00000080
928 #define VIVS_PE_ALPHA_OP_ALPHA_REF__MASK			0x0000ff00
929 #define VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT			8
930 #define VIVS_PE_ALPHA_OP_ALPHA_REF(x)				(((x) << VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_REF__MASK)
931 #define VIVS_PE_ALPHA_OP_ALPHA_REF_MASKFUNC_MASK		0x00010000
932 
933 #define VIVS_PE_ALPHA_BLEND_COLOR				0x00001424
934 #define VIVS_PE_ALPHA_BLEND_COLOR_B__MASK			0x000000ff
935 #define VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT			0
936 #define VIVS_PE_ALPHA_BLEND_COLOR_B(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_B__MASK)
937 #define VIVS_PE_ALPHA_BLEND_COLOR_G__MASK			0x0000ff00
938 #define VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT			8
939 #define VIVS_PE_ALPHA_BLEND_COLOR_G(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_G__MASK)
940 #define VIVS_PE_ALPHA_BLEND_COLOR_R__MASK			0x00ff0000
941 #define VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT			16
942 #define VIVS_PE_ALPHA_BLEND_COLOR_R(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_R__MASK)
943 #define VIVS_PE_ALPHA_BLEND_COLOR_A__MASK			0xff000000
944 #define VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT			24
945 #define VIVS_PE_ALPHA_BLEND_COLOR_A(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_A__MASK)
946 
947 #define VIVS_PE_ALPHA_CONFIG					0x00001428
948 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR			0x00000001
949 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR_MASK		0x00000002
950 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR_MASK		0x00000004
951 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR_MASK		0x00000008
952 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK		0x000000f0
953 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT		4
954 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK)
955 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK		0x00000f00
956 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT		8
957 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK)
958 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK			0x00007000
959 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT			12
960 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK)
961 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR_MASK			0x00008000
962 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA		0x00010000
963 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA_MASK		0x00020000
964 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA_MASK		0x00040000
965 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK		0x00080000
966 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK		0x00f00000
967 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT		20
968 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK)
969 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK		0x0f000000
970 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT		24
971 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK)
972 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK			0x70000000
973 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT			28
974 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK)
975 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA_MASK			0x80000000
976 
977 #define VIVS_PE_COLOR_FORMAT					0x0000142c
978 #define VIVS_PE_COLOR_FORMAT_FORMAT__MASK			0x0000000f
979 #define VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT			0
980 #define VIVS_PE_COLOR_FORMAT_FORMAT(x)				(((x) << VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT__MASK)
981 #define VIVS_PE_COLOR_FORMAT_FORMAT_MASK			0x00000010
982 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK			0x00000f00
983 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT			8
984 #define VIVS_PE_COLOR_FORMAT_COMPONENTS(x)			(((x) << VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT) & VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK)
985 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW			0x00002000
986 #define VIVS_PE_COLOR_FORMAT_COMPONENTS_MASK			0x00001000
987 #define VIVS_PE_COLOR_FORMAT_OVERWRITE				0x00010000
988 #define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK			0x00020000
989 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED			0x00100000
990 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_MASK			0x00200000
991 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK			0x7f000000
992 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT			24
993 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT(x)			(((x) << VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK)
994 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT_MASK			0x80000000
995 
996 #define VIVS_PE_COLOR_ADDR					0x00001430
997 
998 #define VIVS_PE_COLOR_STRIDE					0x00001434
999 
1000 #define VIVS_PE_HDEPTH_CONTROL					0x00001454
1001 #define VIVS_PE_HDEPTH_CONTROL_FORMAT__MASK			0x0000000f
1002 #define VIVS_PE_HDEPTH_CONTROL_FORMAT__SHIFT			0
1003 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED			0x00000000
1004 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D16			0x00000005
1005 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D24S8			0x00000008
1006 
1007 #define VIVS_PE_HDEPTH_ADDR					0x00001458
1008 
1009 #define VIVS_PE_UNK0145C					0x0000145c
1010 
1011 #define VIVS_PE_PIPE(i0)				       (0x00000000 + 0x4*(i0))
1012 #define VIVS_PE_PIPE__ESIZE					0x00000004
1013 #define VIVS_PE_PIPE__LEN					0x00000008
1014 
1015 #define VIVS_PE_PIPE_COLOR_ADDR(i0)			       (0x00001460 + 0x4*(i0))
1016 
1017 #define VIVS_PE_PIPE_DEPTH_ADDR(i0)			       (0x00001480 + 0x4*(i0))
1018 
1019 #define VIVS_PE_PIPE_ADDR_UNK01500(i0)			       (0x00001500 + 0x4*(i0))
1020 
1021 #define VIVS_PE_PIPE_ADDR_UNK01520(i0)			       (0x00001520 + 0x4*(i0))
1022 
1023 #define VIVS_PE_PIPE_ADDR_UNK01540(i0)			       (0x00001540 + 0x4*(i0))
1024 
1025 #define VIVS_PE_STENCIL_CONFIG_EXT				0x000014a0
1026 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK		0x000000ff
1027 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT		0
1028 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x)			(((x) << VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK)
1029 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK_MASK		0x00000100
1030 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16_MASK			0x00000200
1031 #define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__MASK	0xffff0000
1032 #define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__SHIFT	16
1033 #define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF(x)		(((x) << VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__MASK)
1034 
1035 #define VIVS_PE_LOGIC_OP					0x000014a4
1036 #define VIVS_PE_LOGIC_OP_OP__MASK				0x0000000f
1037 #define VIVS_PE_LOGIC_OP_OP__SHIFT				0
1038 #define VIVS_PE_LOGIC_OP_OP(x)					(((x) << VIVS_PE_LOGIC_OP_OP__SHIFT) & VIVS_PE_LOGIC_OP_OP__MASK)
1039 #define VIVS_PE_LOGIC_OP_OP_MASK				0x00000010
1040 #define VIVS_PE_LOGIC_OP_DITHER_MODE__MASK			0x00000060
1041 #define VIVS_PE_LOGIC_OP_DITHER_MODE__SHIFT			5
1042 #define VIVS_PE_LOGIC_OP_DITHER_MODE(x)				(((x) << VIVS_PE_LOGIC_OP_DITHER_MODE__SHIFT) & VIVS_PE_LOGIC_OP_DITHER_MODE__MASK)
1043 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER_MASK			0x00000080
1044 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK			0x00000300
1045 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT			8
1046 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER(x)			(((x) << VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT) & VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK)
1047 #define VIVS_PE_LOGIC_OP_DITHER_MODE_MASK			0x00000400
1048 #define VIVS_PE_LOGIC_OP_UNK11					0x00000800
1049 #define VIVS_PE_LOGIC_OP_UNK20__MASK				0x00300000
1050 #define VIVS_PE_LOGIC_OP_UNK20__SHIFT				20
1051 #define VIVS_PE_LOGIC_OP_UNK20(x)				(((x) << VIVS_PE_LOGIC_OP_UNK20__SHIFT) & VIVS_PE_LOGIC_OP_UNK20__MASK)
1052 #define VIVS_PE_LOGIC_OP_UNK20_MASK				0x00800000
1053 #define VIVS_PE_LOGIC_OP_UNK24__MASK				0x07000000
1054 #define VIVS_PE_LOGIC_OP_UNK24__SHIFT				24
1055 #define VIVS_PE_LOGIC_OP_UNK24(x)				(((x) << VIVS_PE_LOGIC_OP_UNK24__SHIFT) & VIVS_PE_LOGIC_OP_UNK24__MASK)
1056 #define VIVS_PE_LOGIC_OP_UNK24_MASK				0x08000000
1057 #define VIVS_PE_LOGIC_OP_SRGB_MASK				0x40000000
1058 #define VIVS_PE_LOGIC_OP_SRGB					0x80000000
1059 
1060 #define VIVS_PE_DITHER(i0)				       (0x000014a8 + 0x4*(i0))
1061 #define VIVS_PE_DITHER__ESIZE					0x00000004
1062 #define VIVS_PE_DITHER__LEN					0x00000002
1063 
1064 #define VIVS_PE_ALPHA_COLOR_EXT0				0x000014b0
1065 #define VIVS_PE_ALPHA_COLOR_EXT0_B__MASK			0x0000ffff
1066 #define VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT			0
1067 #define VIVS_PE_ALPHA_COLOR_EXT0_B(x)				(((x) << VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_B__MASK)
1068 #define VIVS_PE_ALPHA_COLOR_EXT0_G__MASK			0xffff0000
1069 #define VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT			16
1070 #define VIVS_PE_ALPHA_COLOR_EXT0_G(x)				(((x) << VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_G__MASK)
1071 
1072 #define VIVS_PE_ALPHA_COLOR_EXT1				0x000014b4
1073 #define VIVS_PE_ALPHA_COLOR_EXT1_R__MASK			0x0000ffff
1074 #define VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT			0
1075 #define VIVS_PE_ALPHA_COLOR_EXT1_R(x)				(((x) << VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_R__MASK)
1076 #define VIVS_PE_ALPHA_COLOR_EXT1_A__MASK			0xffff0000
1077 #define VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT			16
1078 #define VIVS_PE_ALPHA_COLOR_EXT1_A(x)				(((x) << VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_A__MASK)
1079 
1080 #define VIVS_PE_STENCIL_CONFIG_EXT2				0x000014b8
1081 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK		0x000000ff
1082 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT		0
1083 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(x)		(((x) << VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK)
1084 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK	0x0000ff00
1085 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT	8
1086 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(x)		(((x) << VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK)
1087 
1088 #define VIVS_PE_MEM_CONFIG					0x000014bc
1089 #define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__MASK			0x01000000
1090 #define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__SHIFT			24
1091 #define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(x)			(((x) << VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__MASK)
1092 #define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__MASK			0x04000000
1093 #define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__SHIFT			26
1094 #define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(x)			(((x) << VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__MASK)
1095 
1096 #define VIVS_PE_HALTI4_UNK014C0					0x000014c0
1097 
1098 #define VIVS_PE_ROBUSTNESS_UNK014C4				0x000014c4
1099 
1100 #define VIVS_PE_UNK01580(i0)				       (0x00001580 + 0x4*(i0))
1101 #define VIVS_PE_UNK01580__ESIZE					0x00000004
1102 #define VIVS_PE_UNK01580__LEN					0x00000003
1103 
1104 #define VIVS_PE_RT_ADDR(i0)				       (0x00000000 + 0x20*(i0))
1105 #define VIVS_PE_RT_ADDR__ESIZE					0x00000020
1106 #define VIVS_PE_RT_ADDR__LEN					0x00000008
1107 
1108 #define VIVS_PE_RT_ADDR_PIPE(i0, i1)			       (0x00014800 + 0x20*(i0) + 0x4*(i1))
1109 #define VIVS_PE_RT_ADDR_PIPE__ESIZE				0x00000004
1110 #define VIVS_PE_RT_ADDR_PIPE__LEN				0x00000008
1111 
1112 #define VIVS_PE_RT_CONFIG(i0)				       (0x00014900 + 0x4*(i0))
1113 #define VIVS_PE_RT_CONFIG__ESIZE				0x00000004
1114 #define VIVS_PE_RT_CONFIG__LEN					0x00000008
1115 #define VIVS_PE_RT_CONFIG_STRIDE__MASK				0x0000ffff
1116 #define VIVS_PE_RT_CONFIG_STRIDE__SHIFT				0
1117 #define VIVS_PE_RT_CONFIG_STRIDE(x)				(((x) << VIVS_PE_RT_CONFIG_STRIDE__SHIFT) & VIVS_PE_RT_CONFIG_STRIDE__MASK)
1118 #define VIVS_PE_RT_CONFIG_FORMAT__MASK				0x001f0000
1119 #define VIVS_PE_RT_CONFIG_FORMAT__SHIFT				16
1120 #define VIVS_PE_RT_CONFIG_FORMAT(x)				(((x) << VIVS_PE_RT_CONFIG_FORMAT__SHIFT) & VIVS_PE_RT_CONFIG_FORMAT__MASK)
1121 #define VIVS_PE_RT_CONFIG_SUPER_TILED				0x04000000
1122 #define VIVS_PE_RT_CONFIG_UNK28					0x10000000
1123 
1124 #define VIVS_PE_HALTI5_UNK14920(i0)			       (0x00014920 + 0x4*(i0))
1125 #define VIVS_PE_HALTI5_UNK14920__ESIZE				0x00000004
1126 #define VIVS_PE_HALTI5_UNK14920__LEN				0x00000007
1127 #define VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK		0x000000f0
1128 #define VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT		4
1129 #define VIVS_PE_HALTI5_UNK14920_COMPONENTS(x)			(((x) << VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT) & VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK)
1130 #define VIVS_PE_HALTI5_UNK14920_UNK8				0x00000100
1131 
1132 #define VIVS_PE_HALTI5_UNK14940(i0)			       (0x00014940 + 0x4*(i0))
1133 #define VIVS_PE_HALTI5_UNK14940__ESIZE				0x00000004
1134 #define VIVS_PE_HALTI5_UNK14940__LEN				0x00000007
1135 
1136 #define VIVS_PE_HALTI5_UNK14960(i0)			       (0x00014960 + 0x4*(i0))
1137 #define VIVS_PE_HALTI5_UNK14960__ESIZE				0x00000004
1138 #define VIVS_PE_HALTI5_UNK14960__LEN				0x00000007
1139 
1140 #define VIVS_PE_HALTI5_UNK14980(i0)			       (0x00014980 + 0x4*(i0))
1141 #define VIVS_PE_HALTI5_UNK14980__ESIZE				0x00000004
1142 #define VIVS_PE_HALTI5_UNK14980__LEN				0x00000007
1143 
1144 #define VIVS_PE_HALTI5_UNK149A0(i0)			       (0x000149a0 + 0x4*(i0))
1145 #define VIVS_PE_HALTI5_UNK149A0__ESIZE				0x00000004
1146 #define VIVS_PE_HALTI5_UNK149A0__LEN				0x00000007
1147 
1148 #define VIVS_PE_ROBUSTNESS_UNK149C0(i0)			       (0x000149c0 + 0x4*(i0))
1149 #define VIVS_PE_ROBUSTNESS_UNK149C0__ESIZE			0x00000004
1150 #define VIVS_PE_ROBUSTNESS_UNK149C0__LEN			0x00000008
1151 
1152 #define VIVS_CO							0x00000000
1153 
1154 #define VIVS_CO_UNK03008					0x00003008
1155 
1156 #define VIVS_CO_KICKER						0x0000300c
1157 
1158 #define VIVS_CO_UNK03010					0x00003010
1159 
1160 #define VIVS_CO_UNK03014					0x00003014
1161 
1162 #define VIVS_CO_UNK03018					0x00003018
1163 
1164 #define VIVS_CO_UNK0301C					0x0000301c
1165 
1166 #define VIVS_CO_UNK03020					0x00003020
1167 
1168 #define VIVS_CO_UNK03024					0x00003024
1169 
1170 #define VIVS_CO_UNK03040					0x00003040
1171 
1172 #define VIVS_CO_UNK03044					0x00003044
1173 
1174 #define VIVS_CO_UNK03048					0x00003048
1175 
1176 #define VIVS_CO_ICACHE_UNK0304C					0x0000304c
1177 
1178 #define VIVS_CO_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
1179 #define VIVS_CO_SAMPLER__ESIZE					0x00000004
1180 #define VIVS_CO_SAMPLER__LEN					0x00000008
1181 
1182 #define VIVS_CO_SAMPLER_UNK03060(i0)			       (0x00003060 + 0x4*(i0))
1183 
1184 #define VIVS_CO_SAMPLER_UNK03080(i0)			       (0x00003080 + 0x4*(i0))
1185 
1186 #define VIVS_CO_SAMPLER_UNK030A0(i0)			       (0x000030a0 + 0x4*(i0))
1187 
1188 #define VIVS_CO_SAMPLER_UNK030C0(i0)			       (0x000030c0 + 0x4*(i0))
1189 
1190 #define VIVS_CO_SAMPLER_UNK030E0(i0)			       (0x000030e0 + 0x4*(i0))
1191 
1192 #define VIVS_CO_SAMPLER_UNK03100(i0)			       (0x00003100 + 0x4*(i0))
1193 
1194 #define VIVS_CO_SAMPLER_UNK03120(i0)			       (0x00003120 + 0x4*(i0))
1195 
1196 #define VIVS_CO_SAMPLER_UNK03140(i0)			       (0x00003140 + 0x4*(i0))
1197 
1198 #define VIVS_CO_SAMPLER_UNK03160(i0)			       (0x00003160 + 0x4*(i0))
1199 
1200 #define VIVS_CO_SAMPLER_UNK03180(i0)			       (0x00003180 + 0x4*(i0))
1201 
1202 #define VIVS_CO_SAMPLER_UNK031A0(i0)			       (0x000031a0 + 0x4*(i0))
1203 
1204 #define VIVS_CO_SAMPLER_UNK031C0(i0)			       (0x000031c0 + 0x4*(i0))
1205 
1206 #define VIVS_CO_SAMPLER_UNK031E0(i0)			       (0x000031e0 + 0x4*(i0))
1207 
1208 #define VIVS_CO_ADDR_UNK03200(i0)			       (0x00003200 + 0x20*(i0))
1209 #define VIVS_CO_ADDR_UNK03200__ESIZE				0x00000020
1210 #define VIVS_CO_ADDR_UNK03200__LEN				0x00000008
1211 
1212 #define VIVS_CO_ADDR_UNK03200_PPIPE(i0, i1)		       (0x00003200 + 0x20*(i0) + 0x4*(i1))
1213 #define VIVS_CO_ADDR_UNK03200_PPIPE__ESIZE			0x00000004
1214 #define VIVS_CO_ADDR_UNK03200_PPIPE__LEN			0x00000008
1215 
1216 #define VIVS_RS							0x00000000
1217 
1218 #define VIVS_RS_KICKER						0x00001600
1219 
1220 #define VIVS_RS_CONFIG						0x00001604
1221 #define VIVS_RS_CONFIG_SOURCE_FORMAT__MASK			0x0000001f
1222 #define VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT			0
1223 #define VIVS_RS_CONFIG_SOURCE_FORMAT(x)				(((x) << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_RS_CONFIG_SOURCE_FORMAT__MASK)
1224 #define VIVS_RS_CONFIG_DOWNSAMPLE_X				0x00000020
1225 #define VIVS_RS_CONFIG_DOWNSAMPLE_Y				0x00000040
1226 #define VIVS_RS_CONFIG_SOURCE_TILED				0x00000080
1227 #define VIVS_RS_CONFIG_DEST_FORMAT__MASK			0x00001f00
1228 #define VIVS_RS_CONFIG_DEST_FORMAT__SHIFT			8
1229 #define VIVS_RS_CONFIG_DEST_FORMAT(x)				(((x) << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT) & VIVS_RS_CONFIG_DEST_FORMAT__MASK)
1230 #define VIVS_RS_CONFIG_DEST_TILED				0x00004000
1231 #define VIVS_RS_CONFIG_SWAP_RB					0x20000000
1232 #define VIVS_RS_CONFIG_FLIP					0x40000000
1233 
1234 #define VIVS_RS_SOURCE_ADDR					0x00001608
1235 
1236 #define VIVS_RS_SOURCE_STRIDE					0x0000160c
1237 #define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK			0x0003ffff
1238 #define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT			0
1239 #define VIVS_RS_SOURCE_STRIDE_STRIDE(x)				(((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK)
1240 #define VIVS_RS_SOURCE_STRIDE_UNK29				0x20000000
1241 #define VIVS_RS_SOURCE_STRIDE_MULTI				0x40000000
1242 #define VIVS_RS_SOURCE_STRIDE_TILING				0x80000000
1243 
1244 #define VIVS_RS_DEST_ADDR					0x00001610
1245 
1246 #define VIVS_RS_DEST_STRIDE					0x00001614
1247 #define VIVS_RS_DEST_STRIDE_STRIDE__MASK			0x0003ffff
1248 #define VIVS_RS_DEST_STRIDE_STRIDE__SHIFT			0
1249 #define VIVS_RS_DEST_STRIDE_STRIDE(x)				(((x) << VIVS_RS_DEST_STRIDE_STRIDE__SHIFT) & VIVS_RS_DEST_STRIDE_STRIDE__MASK)
1250 #define VIVS_RS_DEST_STRIDE_MULTI				0x40000000
1251 #define VIVS_RS_DEST_STRIDE_TILING				0x80000000
1252 
1253 #define VIVS_RS_WINDOW_SIZE					0x00001620
1254 #define VIVS_RS_WINDOW_SIZE_HEIGHT__MASK			0xffff0000
1255 #define VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT			16
1256 #define VIVS_RS_WINDOW_SIZE_HEIGHT(x)				(((x) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_RS_WINDOW_SIZE_HEIGHT__MASK)
1257 #define VIVS_RS_WINDOW_SIZE_WIDTH__MASK				0x0000ffff
1258 #define VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT			0
1259 #define VIVS_RS_WINDOW_SIZE_WIDTH(x)				(((x) << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_RS_WINDOW_SIZE_WIDTH__MASK)
1260 
1261 #define VIVS_RS_DITHER(i0)				       (0x00001630 + 0x4*(i0))
1262 #define VIVS_RS_DITHER__ESIZE					0x00000004
1263 #define VIVS_RS_DITHER__LEN					0x00000002
1264 
1265 #define VIVS_RS_CLEAR_CONTROL					0x0000163c
1266 #define VIVS_RS_CLEAR_CONTROL_BITS__MASK			0x0000ffff
1267 #define VIVS_RS_CLEAR_CONTROL_BITS__SHIFT			0
1268 #define VIVS_RS_CLEAR_CONTROL_BITS(x)				(((x) << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT) & VIVS_RS_CLEAR_CONTROL_BITS__MASK)
1269 #define VIVS_RS_CLEAR_CONTROL_MODE__MASK			0x00030000
1270 #define VIVS_RS_CLEAR_CONTROL_MODE__SHIFT			16
1271 #define VIVS_RS_CLEAR_CONTROL_MODE_DISABLED			0x00000000
1272 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1			0x00010000
1273 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4			0x00020000
1274 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4_2			0x00030000
1275 
1276 #define VIVS_RS_FILL_VALUE(i0)				       (0x00001640 + 0x4*(i0))
1277 #define VIVS_RS_FILL_VALUE__ESIZE				0x00000004
1278 #define VIVS_RS_FILL_VALUE__LEN					0x00000004
1279 
1280 #define VIVS_RS_EXTRA_CONFIG					0x000016a0
1281 #define VIVS_RS_EXTRA_CONFIG_AA__MASK				0x00000003
1282 #define VIVS_RS_EXTRA_CONFIG_AA__SHIFT				0
1283 #define VIVS_RS_EXTRA_CONFIG_AA(x)				(((x) << VIVS_RS_EXTRA_CONFIG_AA__SHIFT) & VIVS_RS_EXTRA_CONFIG_AA__MASK)
1284 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK			0x00000300
1285 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT			8
1286 #define VIVS_RS_EXTRA_CONFIG_ENDIAN(x)				(((x) << VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT) & VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK)
1287 #define VIVS_RS_EXTRA_CONFIG_UNK20				0x00100000
1288 #define VIVS_RS_EXTRA_CONFIG_UNK28				0x10000000
1289 
1290 #define VIVS_RS_KICKER_INPLACE					0x000016b0
1291 
1292 #define VIVS_RS_UNK016B4					0x000016b4
1293 
1294 #define VIVS_RS_SINGLE_BUFFER					0x000016b8
1295 #define VIVS_RS_SINGLE_BUFFER_ENABLE				0x00000001
1296 
1297 #define VIVS_RS_PIPE(i0)				       (0x00000000 + 0x4*(i0))
1298 #define VIVS_RS_PIPE__ESIZE					0x00000004
1299 #define VIVS_RS_PIPE__LEN					0x00000008
1300 
1301 #define VIVS_RS_PIPE_SOURCE_ADDR(i0)			       (0x000016c0 + 0x4*(i0))
1302 
1303 #define VIVS_RS_PIPE_DEST_ADDR(i0)			       (0x000016e0 + 0x4*(i0))
1304 
1305 #define VIVS_RS_PIPE_OFFSET(i0)				       (0x00001700 + 0x4*(i0))
1306 #define VIVS_RS_PIPE_OFFSET_X__MASK				0x0000ffff
1307 #define VIVS_RS_PIPE_OFFSET_X__SHIFT				0
1308 #define VIVS_RS_PIPE_OFFSET_X(x)				(((x) << VIVS_RS_PIPE_OFFSET_X__SHIFT) & VIVS_RS_PIPE_OFFSET_X__MASK)
1309 #define VIVS_RS_PIPE_OFFSET_Y__MASK				0xffff0000
1310 #define VIVS_RS_PIPE_OFFSET_Y__SHIFT				16
1311 #define VIVS_RS_PIPE_OFFSET_Y(x)				(((x) << VIVS_RS_PIPE_OFFSET_Y__SHIFT) & VIVS_RS_PIPE_OFFSET_Y__MASK)
1312 
1313 #define VIVS_TS							0x00000000
1314 
1315 #define VIVS_TS_FLUSH_CACHE					0x00001650
1316 #define VIVS_TS_FLUSH_CACHE_FLUSH				0x00000001
1317 
1318 #define VIVS_TS_MEM_CONFIG					0x00001654
1319 #define VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR			0x00000001
1320 #define VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR			0x00000002
1321 #define VIVS_TS_MEM_CONFIG_DEPTH_16BPP				0x00000008
1322 #define VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE			0x00000010
1323 #define VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE			0x00000020
1324 #define VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION			0x00000040
1325 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION			0x00000080
1326 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK	0x00000f00
1327 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT	8
1328 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(x)		(((x) << VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK)
1329 #define VIVS_TS_MEM_CONFIG_UNK12				0x00001000
1330 #define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE			0x00002000
1331 #define VIVS_TS_MEM_CONFIG_STENCIL_ENABLE			0x00004000
1332 #define VIVS_TS_MEM_CONFIG_UNK21				0x00200000
1333 
1334 #define VIVS_TS_COLOR_STATUS_BASE				0x00001658
1335 
1336 #define VIVS_TS_COLOR_SURFACE_BASE				0x0000165c
1337 
1338 #define VIVS_TS_COLOR_CLEAR_VALUE				0x00001660
1339 
1340 #define VIVS_TS_DEPTH_STATUS_BASE				0x00001664
1341 
1342 #define VIVS_TS_DEPTH_SURFACE_BASE				0x00001668
1343 
1344 #define VIVS_TS_DEPTH_CLEAR_VALUE				0x0000166c
1345 
1346 #define VIVS_TS_DEPTH_AUTO_DISABLE_COUNT			0x00001670
1347 
1348 #define VIVS_TS_COLOR_AUTO_DISABLE_COUNT			0x00001674
1349 
1350 #define VIVS_TS_HDEPTH_STATUS_BASE				0x000016a4
1351 
1352 #define VIVS_TS_HDEPTH_CLEAR_VALUE				0x000016a8
1353 
1354 #define VIVS_TS_HDEPTH_SIZE					0x000016ac
1355 
1356 #define VIVS_TS_COLOR_CLEAR_VALUE_EXT				0x000016bc
1357 
1358 #define VIVS_TS_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
1359 #define VIVS_TS_SAMPLER__ESIZE					0x00000004
1360 #define VIVS_TS_SAMPLER__LEN					0x00000008
1361 
1362 #define VIVS_TS_SAMPLER_CONFIG(i0)			       (0x00001720 + 0x4*(i0))
1363 #define VIVS_TS_SAMPLER_CONFIG_ENABLE				0x00000001
1364 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION			0x00000002
1365 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__MASK		0x000000f0
1366 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__SHIFT	4
1367 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT(x)		(((x) << VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__MASK)
1368 #define VIVS_TS_SAMPLER_CONFIG_UNK11__MASK			0x00003800
1369 #define VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT			11
1370 #define VIVS_TS_SAMPLER_CONFIG_UNK11(x)				(((x) << VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT) & VIVS_TS_SAMPLER_CONFIG_UNK11__MASK)
1371 
1372 #define VIVS_TS_SAMPLER_STATUS_BASE(i0)			       (0x00001740 + 0x4*(i0))
1373 
1374 #define VIVS_TS_SAMPLER_CLEAR_VALUE(i0)			       (0x00001760 + 0x4*(i0))
1375 
1376 #define VIVS_TS_SAMPLER_CLEAR_VALUE2(i0)		       (0x00001780 + 0x4*(i0))
1377 
1378 #define VIVS_TS_SAMPLER_SURFACE_BASE(i0)		       (0x00001a80 + 0x4*(i0))
1379 
1380 #define VIVS_TS_RT(i0)					       (0x00000000 + 0x4*(i0))
1381 #define VIVS_TS_RT__ESIZE					0x00000004
1382 #define VIVS_TS_RT__LEN						0x00000008
1383 
1384 #define VIVS_TS_RT_UNK017A0(i0)				       (0x000017a0 + 0x4*(i0))
1385 
1386 #define VIVS_TS_RT_STATUS_BASE(i0)			       (0x000017c0 + 0x4*(i0))
1387 
1388 #define VIVS_TS_RT_SURFACE_BASE(i0)			       (0x000017e0 + 0x4*(i0))
1389 
1390 #define VIVS_TS_RT_CLEAR_VALUE(i0)			       (0x00001a00 + 0x4*(i0))
1391 
1392 #define VIVS_TS_RT_CLEAR_VALUE2(i0)			       (0x00001a20 + 0x4*(i0))
1393 
1394 #define VIVS_TS_RT_UNK01A40(i0)				       (0x00001a40 + 0x4*(i0))
1395 
1396 #define VIVS_YUV						0x00000000
1397 
1398 #define VIVS_YUV_CONFIG						0x00001678
1399 #define VIVS_YUV_CONFIG_ENABLE					0x00000001
1400 #define VIVS_YUV_CONFIG_SOURCE_FORMAT__MASK			0x00000030
1401 #define VIVS_YUV_CONFIG_SOURCE_FORMAT__SHIFT			4
1402 #define VIVS_YUV_CONFIG_SOURCE_FORMAT(x)			(((x) << VIVS_YUV_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_YUV_CONFIG_SOURCE_FORMAT__MASK)
1403 #define VIVS_YUV_CONFIG_UV_SWAP					0x00000100
1404 
1405 #define VIVS_YUV_WINDOW_SIZE					0x0000167c
1406 #define VIVS_YUV_WINDOW_SIZE_HEIGHT__MASK			0xffff0000
1407 #define VIVS_YUV_WINDOW_SIZE_HEIGHT__SHIFT			16
1408 #define VIVS_YUV_WINDOW_SIZE_HEIGHT(x)				(((x) << VIVS_YUV_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_YUV_WINDOW_SIZE_HEIGHT__MASK)
1409 #define VIVS_YUV_WINDOW_SIZE_WIDTH__MASK			0x0000ffff
1410 #define VIVS_YUV_WINDOW_SIZE_WIDTH__SHIFT			0
1411 #define VIVS_YUV_WINDOW_SIZE_WIDTH(x)				(((x) << VIVS_YUV_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_YUV_WINDOW_SIZE_WIDTH__MASK)
1412 
1413 #define VIVS_YUV_Y_BASE						0x00001680
1414 
1415 #define VIVS_YUV_Y_STRIDE					0x00001684
1416 
1417 #define VIVS_YUV_U_BASE						0x00001688
1418 
1419 #define VIVS_YUV_U_STRIDE					0x0000168c
1420 
1421 #define VIVS_YUV_V_BASE						0x00001690
1422 
1423 #define VIVS_YUV_V_STRIDE					0x00001694
1424 
1425 #define VIVS_YUV_DEST_BASE					0x00001698
1426 
1427 #define VIVS_YUV_DEST_STRIDE					0x0000169c
1428 
1429 #define VIVS_TE							0x00000000
1430 
1431 #define VIVS_TE_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
1432 #define VIVS_TE_SAMPLER__ESIZE					0x00000004
1433 #define VIVS_TE_SAMPLER__LEN					0x0000000c
1434 
1435 #define VIVS_TE_SAMPLER_CONFIG0(i0)			       (0x00002000 + 0x4*(i0))
1436 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK			0x00000007
1437 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT			0
1438 #define VIVS_TE_SAMPLER_CONFIG0_TYPE(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK)
1439 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK			0x00000018
1440 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT			3
1441 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK)
1442 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK			0x00000060
1443 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT			5
1444 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK)
1445 #define VIVS_TE_SAMPLER_CONFIG0_MIN__MASK			0x00000180
1446 #define VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT			7
1447 #define VIVS_TE_SAMPLER_CONFIG0_MIN(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIN__MASK)
1448 #define VIVS_TE_SAMPLER_CONFIG0_MIP__MASK			0x00000600
1449 #define VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT			9
1450 #define VIVS_TE_SAMPLER_CONFIG0_MIP(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIP__MASK)
1451 #define VIVS_TE_SAMPLER_CONFIG0_MAG__MASK			0x00001800
1452 #define VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT			11
1453 #define VIVS_TE_SAMPLER_CONFIG0_MAG(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MAG__MASK)
1454 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK			0x0003e000
1455 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
1456 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK)
1457 #define VIVS_TE_SAMPLER_CONFIG0_ROUND_UV			0x00080000
1458 #define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK		0x00300000
1459 #define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT		20
1460 #define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(x)		(((x) << VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK)
1461 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK			0x00c00000
1462 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT			22
1463 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK)
1464 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK		0xff000000
1465 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT		24
1466 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK)
1467 
1468 #define VIVS_TE_SAMPLER_SIZE(i0)			       (0x00002040 + 0x4*(i0))
1469 #define VIVS_TE_SAMPLER_SIZE_WIDTH__MASK			0x0000ffff
1470 #define VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT			0
1471 #define VIVS_TE_SAMPLER_SIZE_WIDTH(x)				(((x) << VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_SIZE_WIDTH__MASK)
1472 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK			0xffff0000
1473 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT			16
1474 #define VIVS_TE_SAMPLER_SIZE_HEIGHT(x)				(((x) << VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK)
1475 
1476 #define VIVS_TE_SAMPLER_LOG_SIZE(i0)			       (0x00002080 + 0x4*(i0))
1477 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK			0x000003ff
1478 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT			0
1479 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(x)			(((x) << VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK)
1480 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK			0x000ffc00
1481 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT			10
1482 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x)			(((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
1483 #define VIVS_TE_SAMPLER_LOG_SIZE_ASTC				0x10000000
1484 #define VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER			0x20000000
1485 #define VIVS_TE_SAMPLER_LOG_SIZE_SRGB				0x80000000
1486 
1487 #define VIVS_TE_SAMPLER_LOD_CONFIG(i0)			       (0x000020c0 + 0x4*(i0))
1488 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE			0x00000001
1489 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK			0x000007fe
1490 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT			1
1491 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK)
1492 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK			0x001ff800
1493 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT			11
1494 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK)
1495 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK			0x7fe00000
1496 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT			21
1497 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK)
1498 
1499 #define VIVS_TE_SAMPLER_UNK02100(i0)			       (0x00002100 + 0x4*(i0))
1500 
1501 #define VIVS_TE_SAMPLER_UNK02140(i0)			       (0x00002140 + 0x4*(i0))
1502 
1503 #define VIVS_TE_SAMPLER_3D_CONFIG(i0)			       (0x00002180 + 0x4*(i0))
1504 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK			0x00003fff
1505 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT			0
1506 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(x)			(((x) << VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK)
1507 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK		0x03ff0000
1508 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT		16
1509 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(x)			(((x) << VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK)
1510 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK			0x30000000
1511 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT			28
1512 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP(x)			(((x) << VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK)
1513 
1514 #define VIVS_TE_SAMPLER_CONFIG1(i0)			       (0x000021c0 + 0x4*(i0))
1515 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK		0x0000003f
1516 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT		0
1517 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
1518 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK			0x00000700
1519 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT		8
1520 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK)
1521 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK			0x00007000
1522 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT		12
1523 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK)
1524 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK			0x00070000
1525 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT		16
1526 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK)
1527 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK			0x00700000
1528 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
1529 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
1530 #define VIVS_TE_SAMPLER_CONFIG1_TS_MODE__MASK			0x00800000
1531 #define VIVS_TE_SAMPLER_CONFIG1_TS_MODE__SHIFT			23
1532 #define VIVS_TE_SAMPLER_CONFIG1_TS_MODE(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_TS_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_TS_MODE__MASK)
1533 #define VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY			0x01000000
1534 #define VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP		0x02000000
1535 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK			0x1c000000
1536 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT			26
1537 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK)
1538 #define VIVS_TE_SAMPLER_CONFIG1_USE_TS				0x40000000
1539 
1540 #define VIVS_TE_SAMPLER_UNK02200(i0)			       (0x00002200 + 0x4*(i0))
1541 
1542 #define VIVS_TE_SAMPLER_UNK02240(i0)			       (0x00002240 + 0x4*(i0))
1543 
1544 #define VIVS_TE_SAMPLER_ASTC0(i0)			       (0x00002280 + 0x4*(i0))
1545 #define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__MASK			0x0000000f
1546 #define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT		0
1547 #define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT(x)			(((x) << VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__MASK)
1548 #define VIVS_TE_SAMPLER_ASTC0_ASTC_SRGB				0x00000010
1549 #define VIVS_TE_SAMPLER_ASTC0_UNK8__MASK			0x0000ff00
1550 #define VIVS_TE_SAMPLER_ASTC0_UNK8__SHIFT			8
1551 #define VIVS_TE_SAMPLER_ASTC0_UNK8(x)				(((x) << VIVS_TE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK8__MASK)
1552 #define VIVS_TE_SAMPLER_ASTC0_UNK16__MASK			0x00ff0000
1553 #define VIVS_TE_SAMPLER_ASTC0_UNK16__SHIFT			16
1554 #define VIVS_TE_SAMPLER_ASTC0_UNK16(x)				(((x) << VIVS_TE_SAMPLER_ASTC0_UNK16__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK16__MASK)
1555 #define VIVS_TE_SAMPLER_ASTC0_UNK24__MASK			0xff000000
1556 #define VIVS_TE_SAMPLER_ASTC0_UNK24__SHIFT			24
1557 #define VIVS_TE_SAMPLER_ASTC0_UNK24(x)				(((x) << VIVS_TE_SAMPLER_ASTC0_UNK24__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK24__MASK)
1558 
1559 #define VIVS_TE_SAMPLER_ASTC1(i0)			       (0x00002300 + 0x4*(i0))
1560 
1561 #define VIVS_TE_SAMPLER_ASTC2(i0)			       (0x00002380 + 0x4*(i0))
1562 
1563 #define VIVS_TE_SAMPLER_ASTC3(i0)			       (0x00002340 + 0x4*(i0))
1564 
1565 #define VIVS_TE_SAMPLER_LOD_ADDR(i0, i1)		       (0x00002400 + 0x4*(i0) + 0x40*(i1))
1566 #define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE				0x00000040
1567 #define VIVS_TE_SAMPLER_LOD_ADDR__LEN				0x0000000e
1568 
1569 #define VIVS_TE_SAMPLER_LINEAR_STRIDE(i0, i1)		       (0x00002c00 + 0x4*(i0) + 0x40*(i1))
1570 #define VIVS_TE_SAMPLER_LINEAR_STRIDE__ESIZE			0x00000040
1571 #define VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN			0x0000000e
1572 
1573 #define VIVS_NTE						0x00000000
1574 
1575 #define VIVS_NTE_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
1576 #define VIVS_NTE_SAMPLER__ESIZE					0x00000004
1577 #define VIVS_NTE_SAMPLER__LEN					0x00000020
1578 
1579 #define VIVS_NTE_SAMPLER_CONFIG0(i0)			       (0x00010000 + 0x4*(i0))
1580 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK			0x00000007
1581 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT			0
1582 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK)
1583 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK			0x00000018
1584 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT			3
1585 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK)
1586 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK			0x00000060
1587 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT			5
1588 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK)
1589 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK			0x00000180
1590 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT			7
1591 #define VIVS_NTE_SAMPLER_CONFIG0_MIN(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK)
1592 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK			0x00000600
1593 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT			9
1594 #define VIVS_NTE_SAMPLER_CONFIG0_MIP(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK)
1595 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK			0x00001800
1596 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT			11
1597 #define VIVS_NTE_SAMPLER_CONFIG0_MAG(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK)
1598 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK			0x0003e000
1599 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
1600 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK)
1601 #define VIVS_NTE_SAMPLER_CONFIG0_ROUND_UV			0x00080000
1602 #define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK		0x00300000
1603 #define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT		20
1604 #define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE(x)		(((x) << VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK)
1605 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK			0x00c00000
1606 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT			22
1607 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK)
1608 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK		0xff000000
1609 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT		24
1610 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK)
1611 
1612 #define VIVS_NTE_SAMPLER_SIZE(i0)			       (0x00010080 + 0x4*(i0))
1613 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK			0x0000ffff
1614 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT			0
1615 #define VIVS_NTE_SAMPLER_SIZE_WIDTH(x)				(((x) << VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK)
1616 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK			0xffff0000
1617 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT			16
1618 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT(x)				(((x) << VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK)
1619 
1620 #define VIVS_NTE_SAMPLER_LOG_SIZE(i0)			       (0x00010100 + 0x4*(i0))
1621 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK			0x000003ff
1622 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT			0
1623 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH(x)			(((x) << VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK)
1624 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK			0x000ffc00
1625 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT			10
1626 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x)			(((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
1627 #define VIVS_NTE_SAMPLER_LOG_SIZE_ASTC				0x10000000
1628 #define VIVS_NTE_SAMPLER_LOG_SIZE_INT_FILTER			0x20000000
1629 #define VIVS_NTE_SAMPLER_LOG_SIZE_SRGB				0x80000000
1630 
1631 #define VIVS_NTE_SAMPLER_LOD_CONFIG(i0)			       (0x00010180 + 0x4*(i0))
1632 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS_ENABLE			0x00000001
1633 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK			0x000007fe
1634 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT			1
1635 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK)
1636 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK			0x001ff800
1637 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT			11
1638 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK)
1639 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK			0x7fe00000
1640 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT			21
1641 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK)
1642 
1643 #define VIVS_NTE_SAMPLER_UNK10200(i0)			       (0x00010200 + 0x4*(i0))
1644 
1645 #define VIVS_NTE_SAMPLER_LINEAR_STRIDE(i0, i1)		       (0x00010280 + 0x4*(i0) + 0x4*(i1))
1646 #define VIVS_NTE_SAMPLER_LINEAR_STRIDE__ESIZE			0x00000004
1647 #define VIVS_NTE_SAMPLER_LINEAR_STRIDE__LEN			0x00000020
1648 
1649 #define VIVS_NTE_SAMPLER_3D_CONFIG(i0)			       (0x00010300 + 0x4*(i0))
1650 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK			0x00003fff
1651 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT			0
1652 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH(x)			(((x) << VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK)
1653 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK		0x03ff0000
1654 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT		16
1655 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH(x)			(((x) << VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK)
1656 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK			0x30000000
1657 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT			28
1658 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP(x)			(((x) << VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK)
1659 
1660 #define VIVS_NTE_SAMPLER_CONFIG1(i0)			       (0x00010380 + 0x4*(i0))
1661 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK		0x0000003f
1662 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT		0
1663 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
1664 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK		0x00000700
1665 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT		8
1666 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK)
1667 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK		0x00007000
1668 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT		12
1669 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK)
1670 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK		0x00070000
1671 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT		16
1672 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK)
1673 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK		0x00700000
1674 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
1675 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
1676 #define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__MASK			0x00800000
1677 #define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__SHIFT			23
1678 #define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__MASK)
1679 #define VIVS_NTE_SAMPLER_CONFIG1_TEXTURE_ARRAY			0x01000000
1680 #define VIVS_NTE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP		0x02000000
1681 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK			0x1c000000
1682 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT			26
1683 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK)
1684 #define VIVS_NTE_SAMPLER_CONFIG1_USE_TS				0x40000000
1685 
1686 #define VIVS_NTE_SAMPLER_UNK10400(i0)			       (0x00010400 + 0x4*(i0))
1687 
1688 #define VIVS_NTE_SAMPLER_UNK10480(i0)			       (0x00010480 + 0x4*(i0))
1689 
1690 #define VIVS_NTE_SAMPLER_ASTC0(i0)			       (0x00010500 + 0x4*(i0))
1691 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK		0x0000000f
1692 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT		0
1693 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(x)			(((x) << VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK)
1694 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB			0x00000010
1695 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK			0x0000ff00
1696 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT			8
1697 #define VIVS_NTE_SAMPLER_ASTC0_UNK8(x)				(((x) << VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK)
1698 #define VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK			0x00ff0000
1699 #define VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT			16
1700 #define VIVS_NTE_SAMPLER_ASTC0_UNK16(x)				(((x) << VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK)
1701 #define VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK			0xff000000
1702 #define VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT			24
1703 #define VIVS_NTE_SAMPLER_ASTC0_UNK24(x)				(((x) << VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK)
1704 
1705 #define VIVS_NTE_SAMPLER_ASTC1(i0)			       (0x00010580 + 0x4*(i0))
1706 
1707 #define VIVS_NTE_SAMPLER_ASTC2(i0)			       (0x00010600 + 0x4*(i0))
1708 
1709 #define VIVS_NTE_SAMPLER_ASTC3(i0)			       (0x00010680 + 0x4*(i0))
1710 
1711 #define VIVS_NTE_SAMPLER_BASELOD(i0)			       (0x00010700 + 0x4*(i0))
1712 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK			0x0000000f
1713 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT			0
1714 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD(x)			(((x) << VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK)
1715 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK			0x00000f00
1716 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT			8
1717 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD(x)			(((x) << VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK)
1718 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE			0x00010000
1719 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK		0x00700000
1720 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT		20
1721 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(x)		(((x) << VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK)
1722 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD_ENABLE			0x00800000
1723 
1724 #define VIVS_NTE_SAMPLER_UNK10780(i0)			       (0x00010780 + 0x4*(i0))
1725 
1726 #define VIVS_NTE_SAMPLER_FRAC_UNK11000(i0)		       (0x00011000 + 0x4*(i0))
1727 
1728 #define VIVS_NTE_SAMPLER_FRAC_UNK11080(i0)		       (0x00011080 + 0x4*(i0))
1729 
1730 #define VIVS_NTE_SAMPLER_FRAC_UNK11100(i0)		       (0x00011100 + 0x4*(i0))
1731 
1732 #define VIVS_NTE_SAMPLER_FRAC_UNK11180(i0)		       (0x00011180 + 0x4*(i0))
1733 
1734 #define VIVS_NTE_SAMPLER_HALTI4_UNK11200(i0)		       (0x00011200 + 0x4*(i0))
1735 
1736 #define VIVS_NTE_SAMPLER_HALTI4_UNK11280(i0)		       (0x00011280 + 0x4*(i0))
1737 
1738 #define VIVS_NTE_SAMPLER_FRAC_UNK11300(i0)		       (0x00011300 + 0x4*(i0))
1739 
1740 #define VIVS_NTE_SAMPLER_ADDR(i0)			       (0x00010800 + 0x40*(i0))
1741 #define VIVS_NTE_SAMPLER_ADDR__ESIZE				0x00000040
1742 #define VIVS_NTE_SAMPLER_ADDR__LEN				0x00000020
1743 
1744 #define VIVS_NTE_SAMPLER_ADDR_LOD(i0, i1)		       (0x00010800 + 0x40*(i0) + 0x4*(i1))
1745 #define VIVS_NTE_SAMPLER_ADDR_LOD__ESIZE			0x00000004
1746 #define VIVS_NTE_SAMPLER_ADDR_LOD__LEN				0x0000000e
1747 
1748 #define VIVS_NTE_UNK12000(i0)				       (0x00012000 + 0x4*(i0))
1749 #define VIVS_NTE_UNK12000__ESIZE				0x00000004
1750 #define VIVS_NTE_UNK12000__LEN					0x00000100
1751 
1752 #define VIVS_NTE_UNK12400(i0)				       (0x00012400 + 0x4*(i0))
1753 #define VIVS_NTE_UNK12400__ESIZE				0x00000004
1754 #define VIVS_NTE_UNK12400__LEN					0x00000100
1755 
1756 #define VIVS_NTE_HALTI3_UNK14C00(i0)			       (0x00014c00 + 0x4*(i0))
1757 #define VIVS_NTE_HALTI3_UNK14C00__ESIZE				0x00000004
1758 #define VIVS_NTE_HALTI3_UNK14C00__LEN				0x00000010
1759 
1760 #define VIVS_NTE_DESCRIPTOR_UNK14C40				0x00014c40
1761 #define VIVS_NTE_DESCRIPTOR_UNK14C40_UNK0			0x00000001
1762 
1763 #define VIVS_NTE_DESCRIPTOR_FLUSH				0x00014c44
1764 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK			0xf0000000
1765 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT			28
1766 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28(x)			(((x) << VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT) & VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK)
1767 
1768 #define VIVS_NTE_DESCRIPTOR_INVALIDATE				0x00014c48
1769 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK		0x000001ff
1770 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT		0
1771 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX(x)			(((x) << VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT) & VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK)
1772 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_UNK29			0x20000000
1773 
1774 #define VIVS_NTE_DESCRIPTOR(i0)				       (0x00000000 + 0x4*(i0))
1775 #define VIVS_NTE_DESCRIPTOR__ESIZE				0x00000004
1776 #define VIVS_NTE_DESCRIPTOR__LEN				0x00000080
1777 
1778 #define VIVS_NTE_DESCRIPTOR_ADDR_MIRROR(i0)		       (0x00015800 + 0x4*(i0))
1779 
1780 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_MIRROR(i0)		       (0x00015a00 + 0x4*(i0))
1781 
1782 #define VIVS_NTE_DESCRIPTOR_ADDR(i0)			       (0x00015c00 + 0x4*(i0))
1783 
1784 #define VIVS_NTE_DESCRIPTOR_TX_CTRL(i0)			       (0x00015e00 + 0x4*(i0))
1785 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__MASK		0x00000001
1786 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__SHIFT		0
1787 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE(x)			(((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__MASK)
1788 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE			0x00000002
1789 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK		0x0000001c
1790 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT		2
1791 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x)			(((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK)
1792 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_COMPRESSION			0x00000040
1793 
1794 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIRROR(i0)	       (0x00016000 + 0x4*(i0))
1795 
1796 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_MIRROR(i0)	       (0x00016200 + 0x4*(i0))
1797 
1798 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIRROR(i0)	       (0x00016400 + 0x4*(i0))
1799 
1800 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_MIRROR(i0)	       (0x00016600 + 0x4*(i0))
1801 
1802 #define VIVS_NTE_DESCRIPTOR_SAMP_ANISOTROPY_MIRROR(i0)	       (0x00016800 + 0x4*(i0))
1803 
1804 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(i0)		       (0x00016c00 + 0x4*(i0))
1805 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK		0x00000007
1806 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT		0
1807 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK)
1808 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK		0x00000038
1809 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT		3
1810 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK)
1811 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK		0x000001c0
1812 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT		6
1813 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK)
1814 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK		0x00000600
1815 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT		9
1816 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK)
1817 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK		0x00001800
1818 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT		11
1819 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK)
1820 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK		0x00006000
1821 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT		13
1822 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK)
1823 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_ENABLE		0x00020000
1824 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK	0x001c0000
1825 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT	18
1826 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC(x)		(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK)
1827 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK21			0x00200000
1828 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK22			0x00400000
1829 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_INT_FILTER		0x00800000
1830 
1831 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(i0)		       (0x00016e00 + 0x4*(i0))
1832 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK1			0x00000002
1833 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_SRGB			0x00000004
1834 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK3			0x00000008
1835 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK		0x00000030
1836 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT		4
1837 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK)
1838 
1839 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX(i0)		       (0x00017000 + 0x4*(i0))
1840 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK		0x0000ffff
1841 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT		0
1842 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX(x)		(((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK)
1843 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK		0xffff0000
1844 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT		16
1845 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN(x)		(((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK)
1846 
1847 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS(i0)		       (0x00017200 + 0x4*(i0))
1848 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK		0x0000ffff
1849 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT		0
1850 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS(x)		(((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK)
1851 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_ENABLE		0x00010000
1852 
1853 #define VIVS_NTE_DESCRIPTOR_SAMP_ANISOTROPY(i0)		       (0x00017400 + 0x4*(i0))
1854 
1855 #define VIVS_SH							0x00000000
1856 
1857 #define VIVS_SH_CONFIG						0x00015600
1858 #define VIVS_SH_CONFIG_RTNE_ROUNDING				0x00000002
1859 #define VIVS_SH_CONFIG_DUAL16					0x00000004
1860 
1861 #define VIVS_SH_UNK20000(i0)				       (0x00020000 + 0x4*(i0))
1862 #define VIVS_SH_UNK20000__ESIZE					0x00000004
1863 #define VIVS_SH_UNK20000__LEN					0x00002000
1864 
1865 #define VIVS_SH_INST_MEM(i0)				       (0x0000c000 + 0x4*(i0))
1866 #define VIVS_SH_INST_MEM__ESIZE					0x00000004
1867 #define VIVS_SH_INST_MEM__LEN					0x00001000
1868 
1869 #define VIVS_SH_INST_MEM_MIRROR(i0)			       (0x00008000 + 0x4*(i0))
1870 #define VIVS_SH_INST_MEM_MIRROR__ESIZE				0x00000004
1871 #define VIVS_SH_INST_MEM_MIRROR__LEN				0x00001000
1872 
1873 #define VIVS_SH_UNIFORMS(i0)				       (0x00030000 + 0x4*(i0))
1874 #define VIVS_SH_UNIFORMS__ESIZE					0x00000004
1875 #define VIVS_SH_UNIFORMS__LEN					0x00000800
1876 
1877 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR(i0)		       (0x00034000 + 0x4*(i0))
1878 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR__ESIZE			0x00000004
1879 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR__LEN			0x00000800
1880 
1881 #define VIVS_SH_HALTI5_UNIFORMS(i0)			       (0x00036000 + 0x4*(i0))
1882 #define VIVS_SH_HALTI5_UNIFORMS__ESIZE				0x00000004
1883 #define VIVS_SH_HALTI5_UNIFORMS__LEN				0x00000800
1884 
1885 
1886 #endif /* STATE_3D_XML */
1887