| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 194 VLD3DUP, enumerator
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| D | ARMInstrNEON.td | 1515 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1516 class VLD3DUP<bits<4> op7_4, string Dt>
1525 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1526 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1527 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1534 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1535 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1536 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
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| D | ARMISelLowering.cpp | 1228 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; in getTargetNodeName()
9962 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; in CombineBaseUpdate()
10131 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
11065 case ARMISD::VLD3DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3155 case ARMISD::VLD3DUP: { in Select()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 1348 (instregex "VLD3DUP(d|q)(8|16|32)$",
1349 "VLD3DUP(d|q)(8|16|32)Pseudo$")>;
1352 (instregex "VLD3DUP(d|q)(8|16|32)_UPD")>;
1354 (instregex "VLD3DUP(d|q)(8|16|32)Pseudo_UPD")>;
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| D | ARMISelLowering.h | 260 VLD3DUP, enumerator
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| D | ARMInstrNEON.td | 1535 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1536 class VLD3DUP<bits<4> op7_4, string Dt>
1546 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1547 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1548 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1555 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1556 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1557 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
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| D | ARMISelLowering.cpp | 1682 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; in getTargetNodeName()
13153 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; in CombineBaseUpdate()
13319 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
14662 case ARMISD::VLD3DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3766 case ARMISD::VLD3DUP: { in Select()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 1341 (instregex "VLD3DUP(d|q)(8|16|32)$",
1342 "VLD3DUP(d|q)(8|16|32)Pseudo$")>;
1345 (instregex "VLD3DUP(d|q)(8|16|32)_UPD")>;
1347 (instregex "VLD3DUP(d|q)(8|16|32)Pseudo_UPD")>;
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| D | ARMISelLowering.h | 303 VLD3DUP, enumerator
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| D | ARMInstrNEON.td | 1517 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1518 class VLD3DUP<bits<4> op7_4, string Dt>
1528 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1529 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1530 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1537 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1538 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1539 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
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| D | ARMISelLowering.cpp | 1781 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; in getTargetNodeName()
14116 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; in CombineBaseUpdate()
14404 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
16343 case ARMISD::VLD3DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 4025 case ARMISD::VLD3DUP: { in Select()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 10320 // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPqAsm_16, VLD3DUP...
11020 // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
11211 // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
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| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 7732 // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
7926 // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
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