| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 195 VLD4DUP, enumerator
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| D | ARMInstrNEON.td | 1560 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1561 class VLD4DUP<bits<4> op7_4, string Dt>
1571 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1572 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1573 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1580 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1581 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1582 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
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| D | ARMISelLowering.cpp | 1229 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; in getTargetNodeName()
9963 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
10134 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
11066 case ARMISD::VLD4DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3163 case ARMISD::VLD4DUP: { in Select()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 1395 (instregex "VLD4DUP(d|q)(8|16|32)$",
1396 "VLD4DUP(d|q)(8|16|32)Pseudo$")>;
1400 (instregex "VLD4DUP(d|q)(8|16|32)_UPD")>;
1402 (instregex "VLD4DUP(d|q)(8|16|32)Pseudo_UPD")>;
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| D | ARMISelLowering.h | 261 VLD4DUP, enumerator
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| D | ARMInstrNEON.td | 1588 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1589 class VLD4DUP<bits<4> op7_4, string Dt>
1599 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1600 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1601 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1608 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1609 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1610 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
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| D | ARMISelLowering.cpp | 1683 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; in getTargetNodeName()
13154 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
13322 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
14663 case ARMISD::VLD4DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3774 case ARMISD::VLD4DUP: { in Select()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 1388 (instregex "VLD4DUP(d|q)(8|16|32)$",
1389 "VLD4DUP(d|q)(8|16|32)Pseudo$")>;
1393 (instregex "VLD4DUP(d|q)(8|16|32)_UPD")>;
1395 (instregex "VLD4DUP(d|q)(8|16|32)Pseudo_UPD")>;
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| D | ARMISelLowering.h | 304 VLD4DUP, enumerator
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| D | ARMInstrNEON.td | 1570 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1571 class VLD4DUP<bits<4> op7_4, string Dt>
1581 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1582 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1583 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1590 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1591 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1592 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
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| D | ARMISelLowering.cpp | 1782 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; in getTargetNodeName()
14117 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
14407 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
16344 case ARMISD::VLD4DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 4033 case ARMISD::VLD4DUP: { in Select()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 9382 // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
11024 // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
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| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 6233 // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
7736 // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
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