| /external/llvm/lib/Target/AMDGPU/ |
| D | R600Schedule.td | 10 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600Schedule.td | 9 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600Schedule.td | 9 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
|
| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | circ_pcr_assert.ll | 5 ; This test also validates that the VLIW Packetizer does not bail out the compilation
|
| /external/llvm/docs/CommandGuide/ |
| D | tblgen.rst | 102 Generate DFA Packetizer for VLIW targets.
|
| /external/swiftshader/third_party/llvm-subzero/ |
| D | CREDITS.TXT | 99 D: Deterministic finite automaton based infrastructure for VLIW packetization
238 D: Implemented DFA-based target independent VLIW packetizer
284 D: Backend for Qualcomm's Hexagon VLIW processor.
|
| /external/llvm/ |
| D | CREDITS.TXT | 100 D: Deterministic finite automaton based infrastructure for VLIW packetization
239 D: Implemented DFA-based target independent VLIW packetizer
285 D: Backend for Qualcomm's Hexagon VLIW processor.
|
| D | CODE_OWNERS.TXT | 107 D: VLIW Instruction Scheduling, Packetization
|
| /external/llvm-project/llvm/ |
| D | CREDITS.TXT | 111 D: Deterministic finite automaton based infrastructure for VLIW packetization
271 D: Implemented DFA-based target independent VLIW packetizer
317 D: Backend for Qualcomm's Hexagon VLIW processor.
|
| D | CODE_OWNERS.TXT | 148 D: VLIW Instruction Scheduling, Packetization
|
| /external/llvm/docs/TableGen/ |
| D | BackEnds.rst | 180 on a VLIW architecture. The class internally generates a deterministic finite
|
| /external/mesa3d/docs/relnotes/ |
| D | 18.1.0.rst | 72 - [R600] Miscompilation of TGSI to VLIW causes artifacts in Gallium
|
| /external/llvm-project/llvm/docs/ |
| D | CodeGenerator.rst | 522 bundles. A MI bundle can model a VLIW group / pack which contains an arbitrary
582 Packing / bundling of MachineInstrs for VLIW architectures should
1620 VLIW Packetizer
1623 In a Very Long Instruction Word (VLIW) architecture, the compiler is responsible
1626 *bundles*. The VLIW packetizer in LLVM is a target-independent mechanism to
1632 Instructions in a VLIW target can typically be mapped to multiple functional
1637 VLIW packetizer parses the instruction classes of a target and generates tables
1656 To generate tables for a VLIW target, add *Target*\ GenDFAPacketizer.inc as a
|
| /external/llvm-project/llvm/docs/CommandGuide/ |
| D | tblgen.rst | 161 Generate DFA Packetizer for VLIW targets.
|
| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | notes.markdown | 377 - **post\_scheduler** - ALU scheduler, handles VLIW packing and
|
| /external/llvm/docs/ |
| D | CodeGenerator.rst | 522 bundles. A MI bundle can model a VLIW group / pack which contains an arbitrary
1581 VLIW Packetizer
1584 In a Very Long Instruction Word (VLIW) architecture, the compiler is responsible
1587 *bundles*. The VLIW packetizer in LLVM is a target-independent mechanism to
1593 Instructions in a VLIW target can typically be mapped to multiple functional
1598 VLIW packetizer parses the instruction classes of a target and generates tables
1617 To generate tables for a VLIW target, add *Target*\ GenDFAPacketizer.inc as a
|
| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 76 VLIW // Scheduling for VLIW targets. enumerator
|
| /external/llvm-project/llvm/test/tools/llvm-readobj/ELF/ |
| D | file-header-machine-types.test | 352 …eaders %t.mmdsp_plus.o | FileCheck %s -DMACHINE="STMicroelectronics 64bit VLIW Data Signal Process…
|
| /external/llvm-project/llvm/docs/TableGen/ |
| D | BackEnds.rst | 190 on a VLIW architecture. The class internally generates a deterministic finite
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 104 VLIW // Scheduling for VLIW targets. enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 102 VLIW // Scheduling for VLIW targets. enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGISel.cpp | 315 if (TLI->getSchedulingPreference() == Sched::VLIW) in createDefaultScheduler()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGISel.cpp | 271 if (TLI->getSchedulingPreference() == Sched::VLIW) in createDefaultScheduler()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGISel.cpp | 270 if (TLI->getSchedulingPreference() == Sched::VLIW) in createDefaultScheduler()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1303 setSchedulingPreference(Sched::VLIW); in HexagonTargetLowering()
|