| /external/llvm/lib/Target/AMDGPU/ |
| D | VIInstructions.td | 44 // VOP2 Instructions
89 // are VOP2 on SI and VOP3 on VI.
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| D | SIInstrFormats.td | 32 field bits<1> VOP2 = 0;
68 let TSFlags{11} = VOP2;
142 let VOP2 = 1;
648 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
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| D | SIDefines.h | 29 VOP2 = 1 << 11, enumerator
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| D | SIInstrInfo.h | 256 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
260 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
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| D | SIInstrInfo.td | 46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
1141 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1191 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1221 // VOP2 without modifiers
1786 VOP2 <op.SI, outs, ins, opName#asm, []>,
1794 VOP2 <op.VI, outs, ins, opName#asm, []>,
2072 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
2080 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
2228 // A VOP2 instruction that is VOP3-only on VI.
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| /external/llvm-project/llvm/docs/ |
| D | AMDGPUInstructionSyntax.rst | 125 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
134 Native 32-bit encoding (*VOP1*, *VOP2* or *VOPC*) _e32
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 54 VOP2 = 1 << 9 variable in Format
640 VOP2 = { variable
715 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, modifiers) in VOP2:
716 opcode(name, gfx7, gfx9, gfx10, Format.VOP2, modifiers, modifiers)
721 opcode(name, gfx7, gfx9, gfx10, Format.VOP2, True, False)
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| D | aco_validate.cpp | 114 else if ((uint32_t)base_format & (uint32_t)Format::VOP2) in validate_ir()
115 base_format = Format::VOP2; in validate_ir()
135 check(base_format == Format::VOP2 || in validate_ir()
144 check(base_format == Format::VOP2 || in validate_ir()
241 instr->format == Format::VOP2 || in validate_ir()
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| D | aco_ir.h | 100 VOP2 = 1 << 9, enumerator
242 assert(format == Format::VOP1 || format == Format::VOP2 || format == Format::VOPC); in asSDWA()
919 || ((uint16_t) format & (uint16_t) Format::VOP2) == (uint16_t) Format::VOP2 in isVALU()
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| D | aco_optimizer.cpp | 2272 new_instr.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 2)); in combine_add_sub_b2i()
2275 … new_instr.reset(create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOP2), 3, 2)); in combine_add_sub_b2i()
2612 …w_instr.reset(create_instruction<VOP2_instruction>(aco_opcode::v_cndmask_b32, Format::VOP2, 3, 1)); in combine_and_subbrev()
2615 …eset(create_instruction<VOP3A_instruction>(aco_opcode::v_cndmask_b32, asVOP3(Format::VOP2), 3, 1)); in combine_and_subbrev()
2689 … instr.reset(create_instruction<VOP3A_instruction>(mul_instr->opcode, asVOP3(Format::VOP2), 2, 1)); in combine_instruction()
2841 …on> new_instr{create_instruction<VOP2_instruction>(aco_opcode::v_cndmask_b32, Format::VOP2, 3, 1)}; in combine_instruction()
3223 new_mad.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 1)); in apply_literals()
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| D | aco_assembler.cpp | 259 case Format::VOP2: { in emit_instruction()
552 if ((uint16_t) instr->format & (uint16_t) Format::VOP2) { in emit_instruction()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 29 field bit VOP2 = 0;
149 let TSFlags{8} = VOP2;
213 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
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| D | VOP2Instructions.td | 10 // VOP2 Classes
76 let VOP2 = 1;
469 // VOP2 Instructions
923 //===------------------------------- VOP2 -------------------------------===//
969 //===------------------------- VOP2 (with name) -------------------------===//
1179 // VOP2 no carry-in, carry-out.
1187 // VOP2 carry-in, carry-out.
1602 // are VOP2 on SI and VOP3 on VI.
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| D | SIDefines.h | 33 VOP2 = 1 << 8, enumerator
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| D | SIInstrInfo.h | 420 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
424 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
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| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 101 VOP1, VOP2, VOP3, VOPC Instructions
107 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | sdwa-vop2-64bit.mir | 5 # No conversion for VOP2 instructions that have only 64-bit encoding
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| D | dpp_combine.mir | 8 # VOP2:
27 ; VOP2
58 # VOP2:
111 ; VOP2
545 # Test instruction which does not have modifiers in VOP2 form but does in DPP form.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 29 field bit VOP2 = 0;
141 let TSFlags{8} = VOP2;
207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
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| D | VOP2Instructions.td | 10 // VOP2 Classes
72 let VOP2 = 1;
458 // VOP2 Instructions
869 //===------------------------------- VOP2 -------------------------------===//
915 //===------------------------- VOP2 (with name) -------------------------===//
1124 // VOP2 no carry-in, carry-out.
1132 // VOP2 carry-in, carry-out.
1526 // are VOP2 on SI and VOP3 on VI.
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| D | SIDefines.h | 33 VOP2 = 1 << 8, enumerator
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| D | SIInstrInfo.h | 414 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
418 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
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| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX1011.rst | 56 VOP2 section in Instructions
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| D | AMDGPUAsmGFX906.rst | 36 VOP2 section in Instructions
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| /external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
| D | literalv216_gfx10.txt | 144 # Packed VOP2
|