Searched refs:VRSHRN (Results 1 – 14 of 14) sorted by relevance
| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans.s | 339 VRSHRN.S32 d26,q13,#8
346 VRSHRN.S32 d24,q12,#8
347 VRSHRN.S32 d28,q14,#8
348 VRSHRN.S32 d30,q15,#8 @ Truncating the last 8 bits
768 VRSHRN.I32 d28,q14,#5 @ Truncating last 11 bits in G0
770 VRSHRN.I32 d30,q15,#5 @ Truncating last 11 bits in G4
776 VRSHRN.I32 d24,q12,#11 @ Truncating last 11 bits in G2
778 VRSHRN.I32 d4,q2,#11 @ Truncating last 11 bits in G6
804 VRSHRN.I32 d10,q5,#11 @ Truncating last 11 bits in G1
805 VRSHRN.I32 d8,q4,#11 @ Truncating last 11 bits in G3
[all …]
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| D | ihevc_resi_trans_32x32_a9q.s | 917 VRSHRN.S32 D8,Q4,#SHIFT_32 @ROUND NARROW R1 -- dual issued in 2nd cycle
958 VRSHRN.S32 D0,Q0,#SHIFT_32 @ Shift by SHIFT and Round the result
1003 VRSHRN.S32 D14,Q8,#SHIFT_32
1041 VRSHRN.S32 D16,Q8,#SHIFT_32 @ dual issue
1091 VRSHRN.S32 D16,Q8,#SHIFT_32 @ duall issue
1136 VRSHRN.S32 D16,Q8,#SHIFT_32 @ dual issue
1179 VRSHRN.S32 D16,Q8,#SHIFT_32
1217 VRSHRN.S32 D16,Q8,#SHIFT_32
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 116 VRSHRN, // ...right narrow enumerator
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| D | ARMScheduleSwift.td | 565 (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN",
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| D | ARMInstrNEON.td | 524 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
5490 // VRSHRN : Vector Rounding Shift Right and Narrow
5491 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
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| D | ARMISelLowering.cpp | 1188 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; in getTargetNodeName()
10638 VShiftOpc = ARMISD::VRSHRN; break; in PerformIntrinsicCombine()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 829 def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VRSHL", "VRSHR", "VRSHRN", "VT…
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| D | ARMScheduleSwift.td | 581 (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN",
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| D | ARMScheduleA57.td | 1116 "VRSHRN")>;
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| D | ARMInstrNEON.td | 5956 // VRSHRN : Vector Rounding Shift Right and Narrow
5957 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 829 def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VRSHL", "VRSHR", "VRSHRN", "VT…
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| D | ARMScheduleSwift.td | 581 (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN",
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| D | ARMScheduleA57.td | 1123 "VRSHRN")>;
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| D | ARMInstrNEON.td | 5958 // VRSHRN : Vector Rounding Shift Right and Narrow
5959 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
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