| /external/llvm/test/CodeGen/X86/ |
| D | vshift-6.ll | 13 ; VSELECT(r, B, count);
17 ; r = VSELECT(r, C, count);
19 ; VSELECT(r, r+r, count);
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| D | 2011-12-15-vec_shift.ll | 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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| D | vselect-avx.ll | 107 ; We shouldn't try to lower this directly using VSELECT because we don't have
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | vshift-6.ll | 15 ; VSELECT(r, B, count);
19 ; r = VSELECT(r, C, count);
21 ; VSELECT(r, r+r, count);
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| D | 2011-12-15-vec_shift.ll | 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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| D | vselect-avx.ll | 127 ; We shouldn't try to lower this directly using VSELECT because we don't have
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 358 VSELECT, enumerator
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| D | BasicTTIImpl.h | 488 ISD = ISD::VSELECT; in getCmpSelInstrCost()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 80 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
98 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
275 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
320 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
777 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1091 case ISD::VSELECT: in PerformDAGCombine()
1593 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1606 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1611 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1614 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 490 VSELECT, enumerator
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 637 VSELECT, enumerator
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 106 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
167 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
352 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
397 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
711 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1046 case ISD::VSELECT: in PerformDAGCombine()
1618 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1633 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1638 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1641 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 106 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
167 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
352 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
397 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
711 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1046 case ISD::VSELECT: in PerformDAGCombine()
1619 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1634 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1639 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1642 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 157 setOperationAction(ISD::VSELECT, T, Custom); in initializeHVXLowering()
204 setTargetDAGCombine(ISD::VSELECT); in initializeHVXLowering()
1552 case ISD::VSELECT: in LowerHvxOperation()
1599 if (Opc == ISD::VSELECT) { in PerformHvxDAGCombine()
1605 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformHvxDAGCombine()
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| D | HexagonISelLowering.cpp | 1576 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1577 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1625 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
2934 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
3003 } else if (Opc == ISD::VSELECT) { in PerformDAGCombine()
3011 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformDAGCombine()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 184 setOperationAction(ISD::VSELECT, T, Custom); in initializeHVXLowering()
266 setTargetDAGCombine(ISD::VSELECT); in initializeHVXLowering()
1707 SDValue VSel = DAG.getNode(ISD::VSELECT, dl, ValTy, Mask, Load, Thru); in LowerHvxMaskedOp()
2051 case ISD::VSELECT: in LowerHvxOperation()
2190 case ISD::VSELECT: { in PerformHvxDAGCombine()
2196 return DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, Ops[2], Ops[1]); in PerformHvxDAGCombine()
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| D | HexagonISelLowering.cpp | 1720 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1721 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1774 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
3105 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
3189 } else if (Opc == ISD::VSELECT) { in PerformDAGCombine()
3197 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformDAGCombine()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 292 case ISD::VSELECT: in LegalizeOp()
689 case ISD::VSELECT: in Expand()
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| D | LegalizeVectorTypes.cpp | 63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
452 case ISD::VSELECT: in ScalarizeVectorOperand()
590 case ISD::VSELECT: in SplitVectorResult()
1481 case ISD::VSELECT: in SplitVectorOperand()
1553 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
1555 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
2068 case ISD::VSELECT: in WidenVectorResult()
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| D | SelectionDAGDumper.cpp | 216 case ISD::VSELECT: return "vselect"; in getOperationName()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 60 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
589 case ISD::VSELECT: in ScalarizeVectorOperand()
826 case ISD::VSELECT: in SplitVectorResult()
1948 case ISD::VSELECT: in SplitVectorOperand()
2048 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
2050 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
2696 case ISD::VSELECT: in WidenVectorResult()
3906 if (N->getOpcode() != ISD::VSELECT) in WidenVSELECTAndMask()
4005 return DAG.getNode(ISD::VSELECT, SDLoc(N), VSelVT, Mask, VSelOp1, VSelOp2); in WidenVSELECTAndMask()
4200 case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break; in WidenVectorOperand()
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| D | SelectionDAGDumper.cpp | 278 case ISD::VSELECT: return "vselect"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 401 case ISD::VSELECT: in LegalizeOp()
863 case ISD::VSELECT: in Expand()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
595 case ISD::VSELECT: in ScalarizeVectorOperand()
882 case ISD::VSELECT: in SplitVectorResult()
2085 case ISD::VSELECT: in SplitVectorOperand()
2184 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
2186 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
2853 case ISD::VSELECT: in WidenVectorResult()
4072 if (N->getOpcode() != ISD::VSELECT) in WidenVSELECTMask()
4364 case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break; in WidenVectorOperand()
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| D | LegalizeVectorOps.cpp | 397 case ISD::VSELECT: in LegalizeOp()
744 case ISD::VSELECT: in Expand()
|