Searched refs:VSLI (Results 1 – 13 of 13) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 132 VSLI, // ...left enumerator
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| D | ARMScheduleSwift.td | 546 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
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| D | ARMInstrNEON.td | 537 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
5543 // VSLI : Vector Shift Left and Insert
5544 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
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| D | ARMISelLowering.cpp | 1198 case ARMISD::VSLI: return "ARMISD::VSLI"; in getTargetNodeName()
10670 VShiftOpc = ARMISD::VSLI; in PerformIntrinsicCombine()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 190 VSLI, enumerator
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| D | AArch64ISelLowering.cpp | 1762 MAKE_CASE(AArch64ISD::VSLI) in getTargetNodeName()
3750 unsigned Opcode = IsShiftRight ? AArch64ISD::VSRI : AArch64ISD::VSLI; in LowerINTRINSIC_WO_CHAIN()
9221 unsigned Inst = IsShiftRight ? AArch64ISD::VSRI : AArch64ISD::VSLI; in tryLowerToSLI()
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| D | AArch64InstrInfo.td | 481 def AArch64vsli : SDNode<"AArch64ISD::VSLI", SDT_AArch64vshiftinsert>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 1127 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;
1131 "VSLI(v16i8|v8i16|v4i32|v2i64)", "VSRI(v16i8|v8i16|v4i32|v2i64)")>;
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| D | ARMScheduleSwift.td | 562 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
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| D | ARMInstrNEON.td | 6011 // VSLI : Vector Shift Left and Insert
6012 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 1120 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;
1124 "VSLI(v16i8|v8i16|v4i32|v2i64)", "VSRI(v16i8|v8i16|v4i32|v2i64)")>;
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| D | ARMScheduleSwift.td | 562 "VBSL", "VBSP", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
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| D | ARMInstrNEON.td | 6009 // VSLI : Vector Shift Left and Insert
6010 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
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