Home
last modified time | relevance | path

Searched refs:VSRL (Results 1 – 25 of 25) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/VE/VELIntrinsics/
Dvsrl.ll6 ;;; We test VSRL*vvl, VSRL*vvl_v, VSRL*vrl, VSRL*vrl_v, VSRL*vil, VSRL*vil_v,
7 ;;; VSRL*vvml_v, VSRL*vrml_v, VSRL*viml_v, PVSRL*vvl, PVSRL*vvl_v, PVSRL*vrl,
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td76 // VSRL - One of the 32 128-bit VSX registers that overlap with the scalar
78 class VSRL<FPR SubReg, string n> : PPCReg<n> {
161 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
175 … [!cast<VSRL>("VSL"#Index), !cast<VSRL>("VSL"#!add(Index, 1))]>,
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h314 X86_INTRINSIC_DATA(avx2_psrl_d, INTR_TYPE_2OP, X86ISD::VSRL, 0),
315 X86_INTRINSIC_DATA(avx2_psrl_q, INTR_TYPE_2OP, X86ISD::VSRL, 0),
316 X86_INTRINSIC_DATA(avx2_psrl_w, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1296 X86_INTRINSIC_DATA(avx512_mask_psrl_d, INTR_TYPE_2OP_MASK, X86ISD::VSRL, 0),
1297 X86_INTRINSIC_DATA(avx512_mask_psrl_d_128, INTR_TYPE_2OP_MASK, X86ISD::VSRL, 0),
1298 X86_INTRINSIC_DATA(avx512_mask_psrl_d_256, INTR_TYPE_2OP_MASK, X86ISD::VSRL, 0),
1302 X86_INTRINSIC_DATA(avx512_mask_psrl_q, INTR_TYPE_2OP_MASK, X86ISD::VSRL, 0),
1303 X86_INTRINSIC_DATA(avx512_mask_psrl_q_128, INTR_TYPE_2OP_MASK, X86ISD::VSRL, 0),
1304 X86_INTRINSIC_DATA(avx512_mask_psrl_q_256, INTR_TYPE_2OP_MASK, X86ISD::VSRL, 0),
1308 X86_INTRINSIC_DATA(avx512_mask_psrl_w_128, INTR_TYPE_2OP_MASK, X86ISD::VSRL, 0),
[all …]
DX86ISelLowering.h311 VSHL, VSRL, VSRA, enumerator
DX86InstrFragmentsSIMD.td208 def X86vsrl : SDNode<"X86ISD::VSRL",
DX86ISelLowering.cpp17128 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; in getTargetVShiftNode()
19935 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA; in LowerScalarVariableShift()
20202 Opc = X86ISD::VSRL; in LowerShift()
22188 case X86ISD::VSRL: return "X86ISD::VSRL"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h408 X86_INTRINSIC_DATA(avx2_psrl_d, INTR_TYPE_2OP, X86ISD::VSRL, 0),
409 X86_INTRINSIC_DATA(avx2_psrl_q, INTR_TYPE_2OP, X86ISD::VSRL, 0),
410 X86_INTRINSIC_DATA(avx2_psrl_w, INTR_TYPE_2OP, X86ISD::VSRL, 0),
878 X86_INTRINSIC_DATA(avx512_psrl_d_512, INTR_TYPE_2OP, X86ISD::VSRL, 0),
879 X86_INTRINSIC_DATA(avx512_psrl_q_512, INTR_TYPE_2OP, X86ISD::VSRL, 0),
880 X86_INTRINSIC_DATA(avx512_psrl_w_512, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1066 X86_INTRINSIC_DATA(sse2_psrl_d, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1067 X86_INTRINSIC_DATA(sse2_psrl_q, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1068 X86_INTRINSIC_DATA(sse2_psrl_w, INTR_TYPE_2OP, X86ISD::VSRL, 0),
DX86ISelLowering.h309 VSHL, VSRL, VSRA, enumerator
DX86InstrFragmentsSIMD.td227 def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>;
DX86ISelLowering.cpp23272 case X86ISD::VSRL: in getTargetVShiftUniformOpcode()
23274 return IsVariable ? X86ISD::VSRL : X86ISD::VSRLI; in getTargetVShiftUniformOpcode()
29720 case X86ISD::VSRL: return "X86ISD::VSRL"; in getTargetNodeName()
35383 case X86ISD::VSRL: in SimplifyDemandedVectorEltsForTargetNode()
35394 return (UseOpc == X86ISD::VSHL || UseOpc == X86ISD::VSRL || in SimplifyDemandedVectorEltsForTargetNode()
35686 case X86ISD::VSRL: in SimplifyDemandedVectorEltsForTargetNode()
39608 X86ISD::VSRL == N->getOpcode()) && in combineVectorShiftVar()
46031 case X86ISD::VSRL: in PerformDAGCombine()
/external/llvm-project/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h408 X86_INTRINSIC_DATA(avx2_psrl_d, INTR_TYPE_2OP, X86ISD::VSRL, 0),
409 X86_INTRINSIC_DATA(avx2_psrl_q, INTR_TYPE_2OP, X86ISD::VSRL, 0),
410 X86_INTRINSIC_DATA(avx2_psrl_w, INTR_TYPE_2OP, X86ISD::VSRL, 0),
874 X86_INTRINSIC_DATA(avx512_psrl_d_512, INTR_TYPE_2OP, X86ISD::VSRL, 0),
875 X86_INTRINSIC_DATA(avx512_psrl_q_512, INTR_TYPE_2OP, X86ISD::VSRL, 0),
876 X86_INTRINSIC_DATA(avx512_psrl_w_512, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1072 X86_INTRINSIC_DATA(sse2_psrl_d, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1073 X86_INTRINSIC_DATA(sse2_psrl_q, INTR_TYPE_2OP, X86ISD::VSRL, 0),
1074 X86_INTRINSIC_DATA(sse2_psrl_w, INTR_TYPE_2OP, X86ISD::VSRL, 0),
DX86ISelLowering.h351 VSRL, enumerator
DX86InstrFragmentsSIMD.td236 def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>;
DX86ISelLowering.cpp24394 case X86ISD::VSRL: in getTargetVShiftUniformOpcode()
24396 return IsVariable ? X86ISD::VSRL : X86ISD::VSRLI; in getTargetVShiftUniformOpcode()
30860 NODE_NAME_CASE(VSRL) in getTargetNodeName()
37726 case X86ISD::VSRL: in SimplifyDemandedVectorEltsForTargetNode()
37737 return (UseOpc == X86ISD::VSHL || UseOpc == X86ISD::VSRL || in SimplifyDemandedVectorEltsForTargetNode()
38026 case X86ISD::VSRL: in SimplifyDemandedVectorEltsForTargetNode()
42861 X86ISD::VSRL == N->getOpcode()) && in combineVectorShiftVar()
49816 case X86ISD::VSRL: in PerformDAGCombine()
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td74 // VSRL - One of the 32 128-bit VSX registers that overlap with the scalar
76 class VSRL<FPR SubReg, string n> : PPCReg<n> {
138 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td79 // VSRL - One of the 32 128-bit VSX registers that overlap with the scalar
81 class VSRL<FPR SubReg, string n> : PPCReg<n> {
149 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrVec.td567 // e.g. VSLL, VSRL, VSLA, and etc.
1015 // Section 8.12.3 - VSRL (Vector Shift Right Logical)
1016 let cx = 0, cx2 = 0 in defm VSRL : RVSm<"vsrl", 0xf5, I64, V64, VM>;
/external/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td605 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td795 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>;
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td822 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>;
/external/capstone/arch/SystemZ/
DSystemZGenAsmWriter.inc4854 1107322443U, // VSRL
7657 0U, // VSRL
10460 0U, // VSRL
DSystemZGenDisassemblerTables.inc3461 /* 6138 */ MCD_OPC_Decode, 194, 20, 130, 2, // Opcode: VSRL
/external/llvm/test/CodeGen/SystemZ/
Dvec-intrinsics.ll1528 ; VSRL.
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-intrinsics-01.ll1546 ; VSRL.
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc14946 // FastEmit functions for X86ISD::VSRL.
15223 case X86ISD::VSRL: return fastEmit_X86ISD_VSRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);