| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURewriteOutArguments.cpp | 211 auto *VT0 = dyn_cast<FixedVectorType>(Ty0); in isVec3ToVec4Shuffle() local
213 if (!VT0 || !VT1) in isVec3ToVec4Shuffle()
216 if (VT0->getNumElements() != 3 || in isVec3ToVec4Shuffle()
220 return DL->getTypeSizeInBits(VT0->getElementType()) == in isVec3ToVec4Shuffle()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURewriteOutArguments.cpp | 211 VectorType *VT0 = dyn_cast<VectorType>(Ty0); in isVec3ToVec4Shuffle() local
213 if (!VT0 || !VT1) in isVec3ToVec4Shuffle()
216 if (VT0->getNumElements() != 3 || in isVec3ToVec4Shuffle()
220 return DL->getTypeSizeInBits(VT0->getElementType()) == in isVec3ToVec4Shuffle()
|
| /external/kernel-headers/original/uapi/asm-generic/ |
| D | termbits.h | 106 #define VT0 0000000 macro
|
| /external/python/cpython2/Modules/ |
| D | termios.c | 480 #ifdef VT0
481 {"VT0", VT0},
|
| /external/python/cpython2/Lib/plat-irix5/ |
| D | IOCTL.py | 120 VT0 = 0 variable
|
| /external/python/cpython2/Lib/plat-irix6/ |
| D | IOCTL.py | 120 VT0 = 0 variable
|
| /external/python/cpython3/Modules/ |
| D | termios.c | 523 #ifdef VT0
524 {"VT0", VT0},
|
| /external/toybox/toys/pending/ |
| D | stty.c | 107 { "bs0", BS0, BSDLY }, { "bs1", BS1, BSDLY }, { "vt0", VT0, VTDLY },
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 49 for (MVT VT0 : MVT::vector_valuetypes()) { in MipsSETargetLowering() local
51 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
52 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
53 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
54 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
|
| /external/rust/crates/nix/src/sys/ |
| D | termios.rs | 685 VT0 as tcflag_t;
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 75 for (MVT VT0 : MVT::fixedlen_vector_valuetypes()) { in MipsSETargetLowering() local
77 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 75 for (MVT VT0 : MVT::fixedlen_vector_valuetypes()) { in MipsSETargetLowering() local
77 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
|
| /external/minijail/linux-x86/ |
| D | libconstants.gen.c | 5554 #ifdef VT0
5555 { "VT0", (unsigned long) VT0 },
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 3973 EVT VT0 = getSetCCResultType(getSETCCOperandType(SETCC0)); in WidenVSELECTAndMask() local
3975 unsigned ScalarBits0 = VT0.getScalarSizeInBits(); in WidenVSELECTAndMask()
3983 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTAndMask()
3984 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTAndMask()
3993 MaskVT = VT0; in WidenVSELECTAndMask()
3996 SETCC0 = convertMask(SETCC0, VT0, MaskVT); in WidenVSELECTAndMask()
|
| D | DAGCombiner.cpp | 8509 EVT VT0 = N0.getValueType(); in visitSELECT() local
8518 if (VT == VT0 && VT == MVT::i1 && (N0 == N1 || isOneConstant(N1))) in visitSELECT()
8525 if (VT == VT0 && VT == MVT::i1 && isNullConstant(N1)) { in visitSELECT()
8531 if (VT == VT0 && VT == MVT::i1 && isOneConstant(N2)) { in visitSELECT()
8538 if (VT == VT0 && VT == MVT::i1 && (N0 == N2 || isNullConstant(N2))) in visitSELECT()
8545 if (VT0 == MVT::i1) { in visitSELECT()
8667 SDVTList VTs = DAG.getVTList(VT, VT0); in visitSELECT()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 4134 EVT VT0 = getSetCCResultType(getSETCCOperandType(SETCC0)); in WidenVSELECTMask() local
4136 unsigned ScalarBits0 = VT0.getScalarSizeInBits(); in WidenVSELECTMask()
4144 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTMask()
4145 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTMask()
4154 MaskVT = VT0; in WidenVSELECTMask()
4157 SETCC0 = convertMask(SETCC0, VT0, MaskVT); in WidenVSELECTMask()
|
| D | DAGCombiner.cpp | 9199 EVT VT0 = N0.getValueType(); in visitSELECT() local
9208 if (VT == VT0 && VT == MVT::i1 && (N0 == N1 || isOneConstant(N1))) in visitSELECT()
9215 if (VT == VT0 && VT == MVT::i1 && isNullConstant(N1)) { in visitSELECT()
9221 if (VT == VT0 && VT == MVT::i1 && isOneConstant(N2)) { in visitSELECT()
9228 if (VT == VT0 && VT == MVT::i1 && (N0 == N2 || isNullConstant(N2))) in visitSELECT()
9235 if (VT0 == MVT::i1) { in visitSELECT()
9357 SDVTList VTs = DAG.getVTList(VT, VT0); in visitSELECT()
|
| /external/rust/crates/libc/src/unix/redox/ |
| D | mod.rs | 723 pub const VT0: usize = 0o000_000; constant
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 5075 EVT VT0 = N0.getValueType(); in visitSELECT() local
5098 (VT0 == MVT::i1 || (VT0.isInteger() && in visitSELECT()
5105 if (VT == VT0) { in visitSELECT()
5107 return DAG.getNode(ISD::XOR, DL, VT0, in visitSELECT()
5108 N0, DAG.getConstant(1, DL, VT0)); in visitSELECT()
5111 XORNode = DAG.getNode(ISD::XOR, DL0, VT0, in visitSELECT()
5112 N0, DAG.getConstant(1, DL0, VT0)); in visitSELECT()
5114 if (VT.bitsGT(VT0)) in visitSELECT()
5119 if (VT == VT0 && VT == MVT::i1 && isNullConstant(N1)) { in visitSELECT()
5125 if (VT == VT0 && VT == MVT::i1 && isOneConstant(N2)) { in visitSELECT()
[all …]
|
| /external/rust/crates/libc/src/unix/haiku/ |
| D | mod.rs | 1124 pub const VT0: ::tcflag_t = 0x00000000; constant
|
| /external/rust/crates/libc/src/unix/linux_like/ |
| D | mod.rs | 1035 pub const VT0: ::tcflag_t = 0x00000000; constant
|
| /external/rust/crates/libc/src/unix/bsd/apple/ |
| D | mod.rs | 2786 pub const VT0: ::tcflag_t = 0x00000000; constant
|
| /external/rust/crates/libc/src/fuchsia/ |
| D | mod.rs | 1875 pub const VT0: ::c_int = 0x00000000; constant
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 35879 EVT VT0 = BC0.getValueType(); in canonicalizeShuffleMaskWithHorizOp() local
35883 if (Opcode0 != Opcode1 || VT0 != VT1 || VT0.getSizeInBits() != RootSizeInBits) in canonicalizeShuffleMaskWithHorizOp()
35892 if (Mask.size() == VT0.getVectorNumElements()) { in canonicalizeShuffleMaskWithHorizOp()
35893 int NumElts = VT0.getVectorNumElements(); in canonicalizeShuffleMaskWithHorizOp()
35894 int NumLanes = VT0.getSizeInBits() / 128; in canonicalizeShuffleMaskWithHorizOp()
35961 return DAG.getNode(Opcode0, DL, VT0, Lo, Hi); in canonicalizeShuffleMaskWithHorizOp()
43337 EVT VT0 = Op0.getValueType(); in combineAndMaskToShift() local
43340 if (VT0 != VT1 || !VT0.isSimple() || !VT0.isInteger()) in combineAndMaskToShift()
43352 if (!SupportedVectorShiftWithImm(VT0.getSimpleVT(), Subtarget, ISD::SRL)) in combineAndMaskToShift()
43355 unsigned EltBitWidth = VT0.getScalarSizeInBits(); in combineAndMaskToShift()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 34536 EVT VT0 = BC0.getValueType(); in combineTargetShuffle() local
34540 if (Opcode0 == Opcode1 && VT0 == VT1 && in combineTargetShuffle()
34552 SDValue Horiz = DAG.getNode(Opcode0, DL, VT0, Lo, Hi); in combineTargetShuffle()
39980 EVT VT0 = Op0.getValueType(); in combineAndMaskToShift() local
39983 if (VT0 != VT1 || !VT0.isSimple() || !VT0.isInteger()) in combineAndMaskToShift()
39995 if (!SupportedVectorShiftWithImm(VT0.getSimpleVT(), Subtarget, ISD::SRL)) in combineAndMaskToShift()
39998 unsigned EltBitWidth = VT0.getScalarSizeInBits(); in combineAndMaskToShift()
40005 SDValue Shift = DAG.getNode(X86ISD::VSRLI, DL, VT0, Op0, ShAmt); in combineAndMaskToShift()
|