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/external/llvm-project/llvm/test/Transforms/InstCombine/ARM/
Dtbl1.ll27 ; CHECK-NEXT: [[VTBL1:%.*]] = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> [[VEC:%.*]], <8 x i8> …
28 ; CHECK-NEXT: ret <8 x i8> [[VTBL1]]
/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt6581 VTBL1 output:
6582 VTBL1:0:result_int8x8 [] = { 0, fffffff2, fffffff2, fffffff2, 0, 0, fffffff2, fffffff2, }
6583 VTBL1:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
6584 VTBL1:2:result_int32x2 [] = { 33333333, 33333333, }
6585 VTBL1:3:result_int64x1 [] = { 3333333333333333, }
6586 VTBL1:4:result_uint8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
6587 VTBL1:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
6588 VTBL1:6:result_uint32x2 [] = { 33333333, 33333333, }
6589 VTBL1:7:result_uint64x1 [] = { 3333333333333333, }
6590 VTBL1:8:result_poly8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
[all …]
Dref-rvct-neon.txt7533 VTBL1 output:
7534 VTBL1:0:result_int8x8 [] = { 0, fffffff2, fffffff2, fffffff2, 0, 0, fffffff2, fffffff2, }
7535 VTBL1:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
7536 VTBL1:2:result_int32x2 [] = { 33333333, 33333333, }
7537 VTBL1:3:result_int64x1 [] = { 3333333333333333, }
7538 VTBL1:4:result_uint8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
7539 VTBL1:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
7540 VTBL1:6:result_uint32x2 [] = { 33333333, 33333333, }
7541 VTBL1:7:result_uint64x1 [] = { 3333333333333333, }
7542 VTBL1:8:result_poly8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
[all …]
Dref-rvct-all.txt7533 VTBL1 output:
7534 VTBL1:0:result_int8x8 [] = { 0, fffffff2, fffffff2, fffffff2, 0, 0, fffffff2, fffffff2, }
7535 VTBL1:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
7536 VTBL1:2:result_int32x2 [] = { 33333333, 33333333, }
7537 VTBL1:3:result_int64x1 [] = { 3333333333333333, }
7538 VTBL1:4:result_uint8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
7539 VTBL1:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
7540 VTBL1:6:result_uint32x2 [] = { 33333333, 33333333, }
7541 VTBL1:7:result_uint64x1 [] = { 3333333333333333, }
7542 VTBL1:8:result_poly8x8 [] = { 0, f3, f3, f3, 0, 0, f3, f3, }
[all …]
Dexpected_input4gcc-nofp16.txt6784 VTBL1 output:
/external/llvm/lib/Target/ARM/
DARMISelLowering.h159 VTBL1, // 1-register shuffle with mask enumerator
DARMISelDAGToDAG.cpp3693 case ARMISD::VTBL1: { in Select()
3699 ReplaceNode(N, CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops)); in Select()
DARMISelLowering.cpp1214 case ARMISD::VTBL1: return "ARMISD::VTBL1"; in getTargetNodeName()
6191 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, in LowerVECTOR_SHUFFLEv8i8()
DARMInstrNEON.td6442 def VTBL1
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.h200 VTBL1, // 1-register shuffle with mask enumerator
DARMISelLowering.cpp1650 case ARMISD::VTBL1: return "ARMISD::VTBL1"; in getTargetNodeName()
3776 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
7742 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, in LowerVECTOR_SHUFFLEv8i8()
DARMInstrNEON.td543 def NEONvtbl1 : SDNode<"ARMISD::VTBL1", SDTARMVTBL1>;
7003 def VTBL1
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.h203 VTBL1, // 1-register shuffle with mask enumerator
DARMISelLowering.cpp1716 case ARMISD::VTBL1: return "ARMISD::VTBL1"; in getTargetNodeName()
3992 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
8048 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, in LowerVECTOR_SHUFFLEv8i8()
DARMInstrNEON.td533 def NEONvtbl1 : SDNode<"ARMISD::VTBL1", SDTARMVTBL1>;
7054 def VTBL1
/external/clang/include/clang/Basic/
Darm_neon.td729 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc5333 { 0, 0, 0, 0, 0 }, // 501 VTBL1
6380 { 1, 103, 108, 2642, 2645 }, // 501 VTBL1
7427 { 1, 317, 319, 5639, 5642 }, // 501 VTBL1
11249 {DBGFIELD("VTBL1") 1, false, false, 17, 2, 3, 1, 73, 1}, // #501
12698 {DBGFIELD("VTBL1") 1, false, false, 20, 1, 3, 1, 0, 0}, // #501
14147 {DBGFIELD("VTBL1") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #501
15596 {DBGFIELD("VTBL1") 1, false, false, 18, 1, 16, 1, 74, 2}, // #501
17045 {DBGFIELD("VTBL1") 1, false, false, 43, 2, 2, 1, 0, 0}, // #501
DARMGenAsmWriter.inc4361 2690644U, // VTBL1
8585 6784U, // VTBL1
10791 // VTBL1
DARMGenFastISel.inc3402 // FastEmit functions for ARMISD::VTBL1.
3408 return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
5486 case ARMISD::VTBL1: return fastEmit_ARMISD_VTBL1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
DARMGenMCCodeEmitter.inc3669 UINT64_C(4088399872), // VTBL1
10512 case ARM::VTBL1:
20344 CEFBS_HasNEON, // VTBL1 = 3656
DARMGenInstrInfo.inc3671 VTBL1 = 3656,
4751 VTBL1 = 501,
9502 …D::Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3656 = VTBL1
/external/llvm-project/clang/include/clang/Basic/
Darm_neon.td578 def VTBL1 : WInst<"vtbl1", "..p", "UccPc">;
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc2234 2910256U, // VTBL1
5038 320U, // VTBL1
7513 // VTBL1
DARMGenInstrInfo.inc5425 …<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2217 = VTBL1
DARMGenDisassemblerTables.inc3793 /* 7675 */ MCD_OPC_Decode, 169, 17, 134, 1, // Opcode: VTBL1

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