| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 6605 VTBL2 output:
6606 VTBL2:0:result_int8x8 [] = { fffffff6, fffffff3, fffffff3, fffffff3, 0, 0, fffffff3, fffffff3, }
6607 VTBL2:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
6608 VTBL2:2:result_int32x2 [] = { 33333333, 33333333, }
6609 VTBL2:3:result_int64x1 [] = { 3333333333333333, }
6610 VTBL2:4:result_uint8x8 [] = { f6, f5, f5, f5, 0, 0, f5, f5, }
6611 VTBL2:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
6612 VTBL2:6:result_uint32x2 [] = { 33333333, 33333333, }
6613 VTBL2:7:result_uint64x1 [] = { 3333333333333333, }
6614 VTBL2:8:result_poly8x8 [] = { f6, f5, f5, f5, 0, 0, f5, f5, }
[all …]
|
| D | ref-rvct-neon.txt | 7559 VTBL2 output:
7560 VTBL2:0:result_int8x8 [] = { fffffff6, fffffff3, fffffff3, fffffff3, 0, 0, fffffff3, fffffff3, }
7561 VTBL2:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
7562 VTBL2:2:result_int32x2 [] = { 33333333, 33333333, }
7563 VTBL2:3:result_int64x1 [] = { 3333333333333333, }
7564 VTBL2:4:result_uint8x8 [] = { f6, f5, f5, f5, 0, 0, f5, f5, }
7565 VTBL2:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
7566 VTBL2:6:result_uint32x2 [] = { 33333333, 33333333, }
7567 VTBL2:7:result_uint64x1 [] = { 3333333333333333, }
7568 VTBL2:8:result_poly8x8 [] = { f6, f5, f5, f5, 0, 0, f5, f5, }
[all …]
|
| D | ref-rvct-all.txt | 7559 VTBL2 output:
7560 VTBL2:0:result_int8x8 [] = { fffffff6, fffffff3, fffffff3, fffffff3, 0, 0, fffffff3, fffffff3, }
7561 VTBL2:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
7562 VTBL2:2:result_int32x2 [] = { 33333333, 33333333, }
7563 VTBL2:3:result_int64x1 [] = { 3333333333333333, }
7564 VTBL2:4:result_uint8x8 [] = { f6, f5, f5, f5, 0, 0, f5, f5, }
7565 VTBL2:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
7566 VTBL2:6:result_uint32x2 [] = { 33333333, 33333333, }
7567 VTBL2:7:result_uint64x1 [] = { 3333333333333333, }
7568 VTBL2:8:result_poly8x8 [] = { f6, f5, f5, f5, 0, 0, f5, f5, }
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 160 VTBL2, // 2-register shuffle with mask enumerator
|
| D | ARMISelDAGToDAG.cpp | 3671 SelectVTBL(N, false, 2, ARM::VTBL2); in Select()
3702 case ARMISD::VTBL2: { in Select()
3713 ReplaceNode(N, CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops)); in Select()
|
| D | ARMISelLowering.cpp | 1215 case ARMISD::VTBL2: return "ARMISD::VTBL2"; in getTargetNodeName()
6194 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, in LowerVECTOR_SHUFFLEv8i8()
|
| D | ARMInstrNEON.td | 6448 def VTBL2
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 201 VTBL2, // 2-register shuffle with mask enumerator
|
| D | ARMInstrNEON.td | 544 def NEONvtbl2 : SDNode<"ARMISD::VTBL2", SDTARMVTBL2>;
7010 def VTBL2
7065 (v8i8 (VTBL2 (REG_SEQUENCE DPair, v8i8:$Vn0, dsub_0,
|
| D | ARMISelLowering.cpp | 1651 case ARMISD::VTBL2: return "ARMISD::VTBL2"; in getTargetNodeName()
3779 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
7745 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, in LowerVECTOR_SHUFFLEv8i8()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 204 VTBL2, // 2-register shuffle with mask enumerator
|
| D | ARMInstrNEON.td | 534 def NEONvtbl2 : SDNode<"ARMISD::VTBL2", SDTARMVTBL2>;
7061 def VTBL2
7116 (v8i8 (VTBL2 (REG_SEQUENCE DPair, v8i8:$Vn0, dsub_0,
|
| D | ARMISelLowering.cpp | 1717 case ARMISD::VTBL2: return "ARMISD::VTBL2"; in getTargetNodeName()
3995 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
8051 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, in LowerVECTOR_SHUFFLEv8i8()
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 730 def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenSubtargetInfo.inc | 5335 { 0, 0, 0, 0, 0 }, // 503 VTBL2
6382 { 1, 245, 250, 2649, 2653 }, // 503 VTBL2
7429 { 1, 317, 319, 5646, 5650 }, // 503 VTBL2
11251 {DBGFIELD("VTBL2") 1, false, false, 17, 2, 3, 1, 74, 2}, // #503
12700 {DBGFIELD("VTBL2") 1, false, false, 20, 1, 3, 1, 0, 0}, // #503
14149 {DBGFIELD("VTBL2") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #503
15598 {DBGFIELD("VTBL2") 1, false, false, 18, 1, 16, 1, 74, 2}, // #503
17047 {DBGFIELD("VTBL2") 2, false, false, 192, 2, 9, 1, 0, 0}, // #503
|
| D | ARMGenAsmWriter.inc | 4362 2690644U, // VTBL2
8586 6912U, // VTBL2
10798 // VTBL2
|
| D | ARMGenMCCodeEmitter.inc | 3670 UINT64_C(4088400128), // VTBL2
10513 case ARM::VTBL2:
20345 CEFBS_HasNEON, // VTBL2 = 3657
|
| D | ARMGenInstrInfo.inc | 3672 VTBL2 = 3657,
4753 VTBL2 = 503,
9503 …rcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo445, -1 ,nullptr }, // Inst #3657 = VTBL2
|
| /external/llvm-project/clang/include/clang/Basic/ |
| D | arm_neon.td | 579 def VTBL2 : WInst<"vtbl2", ".2p", "UccPc">;
|
| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 2235 2910256U, // VTBL2
5039 328U, // VTBL2
7520 // VTBL2
|
| D | ARMGenInstrInfo.inc | 5426 …raSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo264,0,nullptr }, // Inst #2218 = VTBL2
|
| D | ARMGenDisassemblerTables.inc | 3801 /* 7708 */ MCD_OPC_Decode, 170, 17, 134, 1, // Opcode: VTBL2
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 3217 case ARM::VTBL2: in DecodeTBLInstruction()
|
| /external/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 3644 case ARM::VTBL2: in DecodeTBLInstruction()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 3623 case ARM::VTBL2: in DecodeTBLInstruction()
|