| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_sbr_imdct_using_fft.s | 399 VTRN.32 q12, q5
402 VTRN.32 q9, q2
406 VTRN.32 q0, q7
410 VTRN.32 q14, q4
414 VTRN.32 q13, q6
418 VTRN.32 q10, q3
422 VTRN.32 q1, q8
426 VTRN.32 q15, q11
580 VTRN.32 q0, q4
583 VTRN.32 q2, q6
[all …]
|
| D | ixheaacd_imdct_using_fft.s | 394 VTRN.32 q12, q5
396 VTRN.32 q9, q2
400 VTRN.32 q0, q7
404 VTRN.32 q14, q4
408 VTRN.32 q13, q6
412 VTRN.32 q10, q3
416 VTRN.32 q1, q8
420 VTRN.32 q15, q11
570 VTRN.32 q0, q4
573 VTRN.32 q2, q6
[all …]
|
| D | ixheaacd_fft32x32_ld.s | 402 VTRN.32 q12, q5
405 VTRN.32 q9, q2
409 VTRN.32 q0, q7
413 VTRN.32 q14, q4
417 VTRN.32 q13, q6
421 VTRN.32 q10, q3
425 VTRN.32 q1, q8
429 VTRN.32 q15, q11
583 VTRN.32 q0, q4
586 VTRN.32 q2, q6
[all …]
|
| D | ixheaacd_esbr_cos_sin_mod_loop2.s | 100 VTRN.32 D2, D3
|
| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans_32x32_a9q.s | 132 VTRN.S32 D30,D31 @ D30 - [0 0] [0 1] [16 0] [16 1]
133 VTRN.S16 D30,D31 @ D31 - [8 0] [8 1] [24 0] [24 1]
251 VTRN.S32 D26,D27
269 VTRN.S16 D4,D5
313 VTRN.32 Q15, Q5 @R1 transpose1 -- dual issue
317 VTRN.32 Q4,Q12 @R2 transpose1
318 VTRN.32 Q8,Q2 @R2 transpose1
330 VTRN.32 Q9, Q13 @R1 transpose1
382 VTRN.32 Q2, Q5 @
385 VTRN.32 Q9, Q8 @ 1st cycle dual issued
[all …]
|
| D | ihevc_resi_trans.s | 281 VTRN.16 d10,d11 @ Transpose step 1
287 VTRN.16 d12,d13 @ Transpose step 2
288 VTRN.32 q5,q6 @ Transpose step 3, Residue block transposed
319 VTRN.32 q7,q8
320 VTRN.32 q9,q10
580 VTRN.16 q0,q1 @ Transpose residue matrix step (1a)
582 VTRN.16 q2,q3 @ Transpose residue matrix step (1b)
584 VTRN.16 q4,q5 @ Transpose residue matrix step (1c)
585 VTRN.16 q6,q7 @ Transpose residue matrix step (1d)
586 VTRN.32 q0,q2 @ Transpose residue matrix step (2a)
[all …]
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 3047 VTRN/VTRNQ chunk 0 output:
3048 VTRN/VTRNQ:0:result_int8x8 [] = { fffffff0, fffffff1, 11, 11, fffffff2, fffffff3, 11, 11, }
3049 VTRN/VTRNQ:1:result_int16x4 [] = { fffffff0, fffffff1, 22, 22, }
3050 VTRN/VTRNQ:2:result_int32x2 [] = { fffffff0, fffffff1, }
3051 VTRN/VTRNQ:3:result_int64x1 [] = { 3333333333333333, }
3052 VTRN/VTRNQ:4:result_uint8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, }
3053 VTRN/VTRNQ:5:result_uint16x4 [] = { fff0, fff1, 66, 66, }
3054 VTRN/VTRNQ:6:result_uint32x2 [] = { fffffff0, fffffff1, }
3055 VTRN/VTRNQ:7:result_uint64x1 [] = { 3333333333333333, }
3056 VTRN/VTRNQ:8:result_poly8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, }
[all …]
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| D | ref-rvct-neon.txt | 3475 VTRN/VTRNQ chunk 0 output:
3476 VTRN/VTRNQ:0:result_int8x8 [] = { fffffff0, fffffff1, 11, 11, fffffff2, fffffff3, 11, 11, }
3477 VTRN/VTRNQ:1:result_int16x4 [] = { fffffff0, fffffff1, 22, 22, }
3478 VTRN/VTRNQ:2:result_int32x2 [] = { fffffff0, fffffff1, }
3479 VTRN/VTRNQ:3:result_int64x1 [] = { 3333333333333333, }
3480 VTRN/VTRNQ:4:result_uint8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, }
3481 VTRN/VTRNQ:5:result_uint16x4 [] = { fff0, fff1, 66, 66, }
3482 VTRN/VTRNQ:6:result_uint32x2 [] = { fffffff0, fffffff1, }
3483 VTRN/VTRNQ:7:result_uint64x1 [] = { 3333333333333333, }
3484 VTRN/VTRNQ:8:result_poly8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, }
[all …]
|
| D | ref-rvct-all.txt | 3475 VTRN/VTRNQ chunk 0 output:
3476 VTRN/VTRNQ:0:result_int8x8 [] = { fffffff0, fffffff1, 11, 11, fffffff2, fffffff3, 11, 11, }
3477 VTRN/VTRNQ:1:result_int16x4 [] = { fffffff0, fffffff1, 22, 22, }
3478 VTRN/VTRNQ:2:result_int32x2 [] = { fffffff0, fffffff1, }
3479 VTRN/VTRNQ:3:result_int64x1 [] = { 3333333333333333, }
3480 VTRN/VTRNQ:4:result_uint8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, }
3481 VTRN/VTRNQ:5:result_uint16x4 [] = { fff0, fff1, 66, 66, }
3482 VTRN/VTRNQ:6:result_uint32x2 [] = { fffffff0, fffffff1, }
3483 VTRN/VTRNQ:7:result_uint64x1 [] = { 3333333333333333, }
3484 VTRN/VTRNQ:8:result_poly8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, }
[all …]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | neon-shuffle-encoding.s | 79 @ VTRN alternate size suffices
|
| /external/llvm/test/MC/ARM/ |
| D | neon-shuffle-encoding.s | 79 @ VTRN alternate size suffices
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-trn.ll | 108 ; Undef shuffle indices should not prevent matching to VTRN:
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-trn.ll | 108 ; Undef shuffle indices should not prevent matching to VTRN:
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 158 VTRN, // transpose enumerator
|
| D | ARMScheduleSwift.td | 584 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 199 VTRN, // transpose enumerator
|
| D | ARMScheduleR52.td | 830 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VSWP", "VTRN", "VUZP", "VZIP")…
|
| D | ARMScheduleSwift.td | 600 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 202 VTRN, // transpose enumerator
|
| D | ARMScheduleR52.td | 830 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VSWP", "VTRN", "VUZP", "VZIP")…
|
| D | ARMScheduleSwift.td | 600 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vzip.ll | 67 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
|
| D | vuzp.ll | 67 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | vzip.ll | 68 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
|
| D | vuzp.ll | 68 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
|