| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 3708 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorStores() local
3713 EVT ValVT = ValOp.getValueType(); in GenWidenVectorStores()
3730 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, in GenWidenVectorStores()
3747 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); in GenWidenVectorStores()
3782 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorTruncStores() local
3786 EVT ValVT = ValOp.getValueType(); in GenWidenVectorTruncStores()
3790 assert(StVT.isVector() && ValOp.getValueType().isVector()); in GenWidenVectorTruncStores()
3791 assert(StVT.bitsLT(ValOp.getValueType())); in GenWidenVectorTruncStores()
3800 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, in GenWidenVectorTruncStores()
3813 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, in GenWidenVectorTruncStores()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstPropagation.cpp | 2693 const MachineOperand &ValOp = MI.getOperand(TakeOp); in evaluateHexCondMove() local
2697 if (ValOp.isImm()) { in evaluateHexCondMove()
2698 int64_t V = ValOp.getImm(); in evaluateHexCondMove()
2706 if (ValOp.isReg()) { in evaluateHexCondMove()
2707 RegisterSubReg R(ValOp); in evaluateHexCondMove()
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| D | HexagonSplitDouble.cpp | 643 MachineOperand &ValOp = Load ? MI->getOperand(0) in splitMemRef() local
646 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
|
| D | HexagonBitSimplify.cpp | 1919 MachineOperand &ValOp = MI->getOperand(2); in genStoreUpperHalf() local
1920 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf()
1930 ValOp.setReg(H.Reg); in genStoreUpperHalf()
1931 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonConstPropagation.cpp | 2698 const MachineOperand &ValOp = MI.getOperand(TakeOp); in evaluateHexCondMove() local
2702 if (ValOp.isImm()) { in evaluateHexCondMove()
2703 int64_t V = ValOp.getImm(); in evaluateHexCondMove()
2711 if (ValOp.isReg()) { in evaluateHexCondMove()
2712 RegisterSubReg R(ValOp); in evaluateHexCondMove()
|
| D | HexagonSplitDouble.cpp | 643 MachineOperand &ValOp = Load ? MI->getOperand(0) in splitMemRef() local
646 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
|
| D | HexagonBitSimplify.cpp | 1929 MachineOperand &ValOp = MI->getOperand(2); in genStoreUpperHalf() local
1930 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf()
1940 ValOp.setReg(H.Reg); in genStoreUpperHalf()
1941 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1819 MachineOperand &ValOp = MI->getOperand(2); in genStoreUpperHalf() local
1820 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf()
1830 ValOp.setReg(H.Reg); in genStoreUpperHalf()
1831 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
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| D | HexagonSplitDouble.cpp | 598 MachineOperand &ValOp = Load ? MI->getOperand(0) in splitMemRef() local
601 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 5075 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorStores() local
5080 EVT ValVT = ValOp.getValueType(); in GenWidenVectorStores()
5097 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, in GenWidenVectorStores()
5112 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); in GenWidenVectorStores()
5143 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorTruncStores() local
5147 EVT ValVT = ValOp.getValueType(); in GenWidenVectorTruncStores()
5151 assert(StVT.isVector() && ValOp.getValueType().isVector()); in GenWidenVectorTruncStores()
5152 assert(StVT.bitsLT(ValOp.getValueType())); in GenWidenVectorTruncStores()
5161 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, in GenWidenVectorTruncStores()
5170 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, in GenWidenVectorTruncStores()
|
| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | SROA.cpp | 799 Value *ValOp = SI.getValueOperand(); in visitStoreInst() local
800 if (ValOp == *U) in visitStoreInst()
809 if (isa<ScalableVectorType>(ValOp->getType())) in visitStoreInst()
812 uint64_t Size = DL.getTypeStoreSize(ValOp->getType()).getFixedSize(); in visitStoreInst()
830 assert((!SI.isSimple() || ValOp->getType()->isSingleValueType()) && in visitStoreInst()
832 handleLoadOrStore(ValOp->getType(), SI, Offset, Size, SI.isVolatile()); in visitStoreInst()
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | SROA.cpp | 743 Value *ValOp = SI.getValueOperand(); in visitStoreInst() local
744 if (ValOp == *U) in visitStoreInst()
750 uint64_t Size = DL.getTypeStoreSize(ValOp->getType()); in visitStoreInst()
768 assert((!SI.isSimple() || ValOp->getType()->isSingleValueType()) && in visitStoreInst()
770 handleLoadOrStore(ValOp->getType(), SI, Offset, Size, SI.isVolatile()); in visitStoreInst()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | SROA.cpp | 796 Value *ValOp = SI.getValueOperand(); in visitStoreInst() local
797 if (ValOp == *U) in visitStoreInst()
806 uint64_t Size = DL.getTypeStoreSize(ValOp->getType()); in visitStoreInst()
824 assert((!SI.isSimple() || ValOp->getType()->isSingleValueType()) && in visitStoreInst()
826 handleLoadOrStore(ValOp->getType(), SI, Offset, Size, SI.isVolatile()); in visitStoreInst()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 5232 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorStores() local
5237 EVT ValVT = ValOp.getValueType(); in GenWidenVectorStores()
5260 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, in GenWidenVectorStores()
5276 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); in GenWidenVectorStores()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 790 Operand *ValOp = Intrinsic->getArg(1); in genTargetHelperCallFor() local
791 assert(ValOp->getType() == IceType_i8); in genTargetHelperCallFor()
793 Context.insert<InstCast>(InstCast::Zext, ValExt, ValOp); in genTargetHelperCallFor()
|
| D | IceTargetLoweringARM32.cpp | 789 Operand *ValOp = Intrinsic->getArg(1); in genTargetHelperCallFor() local
790 assert(ValOp->getType() == IceType_i8); in genTargetHelperCallFor()
792 Context.insert<InstCast>(InstCast::Zext, ValExt, ValOp); in genTargetHelperCallFor()
|