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Searched refs:ValReg (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/lib/CodeGen/GlobalISel/
DIRTranslator.cpp38 unsigned &ValReg = ValToVReg[&Val]; in getOrCreateVReg() local
40 if (!ValReg) { in getOrCreateVReg()
48 ValReg = VReg; in getOrCreateVReg()
51 return ValReg; in getOrCreateVReg()
/external/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp109 unsigned ValReg; in EmitTargetCodeForMemset() local
116 ValReg = X86::AX; in EmitTargetCodeForMemset()
121 ValReg = X86::EAX; in EmitTargetCodeForMemset()
126 ValReg = X86::RAX; in EmitTargetCodeForMemset()
132 ValReg = X86::AL; in EmitTargetCodeForMemset()
143 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
DX86FastISel.cpp93 bool X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
501 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore() argument
519 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1); in X86FastEmitStore()
520 ValReg = AndResult; in X86FastEmitStore()
639 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
642 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill)); in X86FastEmitStore()
684 unsigned ValReg = getRegForValue(Val); in X86FastEmitStore() local
685 if (ValReg == 0) in X86FastEmitStore()
689 return X86FastEmitStore(VT, ValReg, ValKill, AM, MMO, Aligned); in X86FastEmitStore()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp110 unsigned ValReg; in EmitTargetCodeForMemset() local
117 ValReg = X86::AX; in EmitTargetCodeForMemset()
122 ValReg = X86::EAX; in EmitTargetCodeForMemset()
127 ValReg = X86::RAX; in EmitTargetCodeForMemset()
133 ValReg = X86::AL; in EmitTargetCodeForMemset()
144 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
DX86FastISel.cpp93 bool X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
483 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore() argument
504 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1); in X86FastEmitStore()
505 ValReg = AndResult; in X86FastEmitStore()
647 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
650 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill)); in X86FastEmitStore()
694 unsigned ValReg = getRegForValue(Val); in X86FastEmitStore() local
695 if (ValReg == 0) in X86FastEmitStore()
699 return X86FastEmitStore(VT, ValReg, ValKill, AM, MMO, Aligned); in X86FastEmitStore()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DCallLowering.cpp510 Register CallLowering::ValueHandler::extendRegister(Register ValReg, in extendRegister() argument
514 LLT ValTy = MRI.getType(ValReg); in extendRegister()
516 return ValReg; in extendRegister()
520 return ValReg; in extendRegister()
530 return ValReg; in extendRegister()
532 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
537 MIRBuilder.buildSExt(NewReg, ValReg); in extendRegister()
542 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
DLegalizerHelper.cpp3737 Register ValReg = MI.getOperand(0).getReg(); in reduceLoadStoreWidth() local
3739 LLT ValTy = MRI.getType(ValReg); in reduceLoadStoreWidth()
3754 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, in reduceLoadStoreWidth()
3807 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, in reduceLoadStoreWidth()
6168 Register ValReg = MI.getOperand(ValRegIndex).getReg(); in lowerReadWriteRegister() local
6169 const LLT Ty = MRI.getType(ValReg); in lowerReadWriteRegister()
6178 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
6180 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
/external/llvm-project/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp115 unsigned ValReg; in EmitTargetCodeForMemset() local
122 ValReg = X86::EAX; in EmitTargetCodeForMemset()
127 ValReg = X86::RAX; in EmitTargetCodeForMemset()
133 ValReg = X86::AX; in EmitTargetCodeForMemset()
138 ValReg = X86::AL; in EmitTargetCodeForMemset()
148 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
DX86FastISel.cpp92 bool X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
482 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore() argument
503 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1); in X86FastEmitStore()
504 ValReg = AndResult; in X86FastEmitStore()
646 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
649 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill)); in X86FastEmitStore()
693 Register ValReg = getRegForValue(Val); in X86FastEmitStore() local
694 if (ValReg == 0) in X86FastEmitStore()
698 return X86FastEmitStore(VT, ValReg, ValKill, AM, MMO, Aligned); in X86FastEmitStore()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DCallLowering.cpp458 Register CallLowering::ValueHandler::extendRegister(Register ValReg, in extendRegister() argument
461 if (LocTy.getSizeInBits() == MRI.getType(ValReg).getSizeInBits()) in extendRegister()
462 return ValReg; in extendRegister()
469 return ValReg; in extendRegister()
471 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
476 MIRBuilder.buildSExt(NewReg, ValReg); in extendRegister()
481 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsCallLowering.cpp232 Register extendRegister(Register ValReg, const CCValAssign &VA);
290 Register MipsOutgoingValueHandler::extendRegister(Register ValReg, in extendRegister() argument
295 return MIRBuilder.buildSExt(LocTy, ValReg).getReg(0); in extendRegister()
298 return MIRBuilder.buildZExt(LocTy, ValReg).getReg(0); in extendRegister()
301 return MIRBuilder.buildAnyExt(LocTy, ValReg).getReg(0); in extendRegister()
305 return ValReg; in extendRegister()
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVExpandAtomicPseudoInsts.cpp380 MachineBasicBlock *MBB, Register ValReg, in insertSext() argument
382 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
383 .addReg(ValReg) in insertSext()
385 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
386 .addReg(ValReg) in insertSext()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp244 Register extendRegister(Register ValReg, const CCValAssign &VA);
321 Register OutgoingValueHandler::extendRegister(Register ValReg, in extendRegister() argument
327 MIRBuilder.buildSExt(ExtReg, ValReg); in extendRegister()
332 MIRBuilder.buildZExt(ExtReg, ValReg); in extendRegister()
337 MIRBuilder.buildAnyExt(ExtReg, ValReg); in extendRegister()
342 return ValReg; in extendRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVExpandPseudoInsts.cpp397 MachineBasicBlock *MBB, Register ValReg, in insertSext() argument
399 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
400 .addReg(ValReg) in insertSext()
402 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
403 .addReg(ValReg) in insertSext()
/external/llvm-project/llvm/lib/Target/ARC/
DARCOptAddrMode.cpp426 Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register(); in canSinkLoadStoreTo() local
435 if (ValReg && MI->readsVirtualRegister(ValReg)) in canSinkLoadStoreTo()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCOptAddrMode.cpp426 Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register(); in canSinkLoadStoreTo() local
435 if (ValReg && MI->readsVirtualRegister(ValReg)) in canSinkLoadStoreTo()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64LegalizerInfo.cpp698 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoadStore() local
699 const LLT ValTy = MRI.getType(ValReg); in legalizeLoadStore()
712 auto Bitcast = MIRBuilder.buildBitcast({NewTy}, {ValReg}); in legalizeLoadStore()
717 MIRBuilder.buildBitcast({ValReg}, {NewLoad}); in legalizeLoadStore()
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp1730 unsigned ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1734 .addReg(ValReg) in EmitInstruction()
1741 .addReg(ValReg) in EmitInstruction()
1744 .addReg(ValReg) in EmitInstruction()
1751 .addReg(ValReg) in EmitInstruction()
1796 unsigned ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1800 .addReg(ValReg) in EmitInstruction()
1810 .addReg(ValReg) in EmitInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp1854 Register ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1858 .addReg(ValReg) in EmitInstruction()
1865 .addReg(ValReg) in EmitInstruction()
1868 .addReg(ValReg) in EmitInstruction()
1875 .addReg(ValReg) in EmitInstruction()
1920 Register ValReg = MI->getOperand(1).getReg(); in EmitInstruction() local
1924 .addReg(ValReg) in EmitInstruction()
1934 .addReg(ValReg) in EmitInstruction()
/external/llvm-project/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp1899 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
1903 .addReg(ValReg) in emitInstruction()
1910 .addReg(ValReg) in emitInstruction()
1913 .addReg(ValReg) in emitInstruction()
1920 .addReg(ValReg) in emitInstruction()
1965 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
1969 .addReg(ValReg) in emitInstruction()
1979 .addReg(ValReg) in emitInstruction()
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64LegalizerInfo.cpp862 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoadStore() local
863 const LLT ValTy = MRI.getType(ValReg); in legalizeLoadStore()
875 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
879 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DCallLowering.h155 Register extendRegister(Register ValReg, CCValAssign &VA);
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DCallLowering.h169 Register extendRegister(Register ValReg, CCValAssign &VA,
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp1274 Register ValReg = MI.getOperand(3).getReg(); in selectDSOrderedIntrinsic() local
1277 .addReg(ValReg) in selectDSOrderedIntrinsic()
2675 Register ValReg = MI.getOperand(2).getReg(); in selectG_INSERT_VECTOR_ELT() local
2679 LLT ValTy = MRI->getType(ValReg); in selectG_INSERT_VECTOR_ELT()
2684 const RegisterBank *ValRB = RBI.getRegBank(ValReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2701 !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2726 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
2736 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
DAMDGPULegalizerInfo.cpp2383 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoad() local
2384 LLT ValTy = MRI.getType(ValReg); in legalizeLoad()
2418 B.buildTrunc(ValReg, WideLoad).getReg(0); in legalizeLoad()
2426 B.buildExtract(ValReg, WideLoad, 0); in legalizeLoad()
2431 WideLoad = Helper.widenWithUnmerge(WideTy, ValReg); in legalizeLoad()

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