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Searched refs:ValVReg (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/llvm/lib/Target/Mips/
DMipsCallLowering.cpp97 void assignValueToReg(Register ValVReg, const CCValAssign &VA,
103 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
137 void MipsIncomingValueHandler::assignValueToReg(Register ValVReg, in assignValueToReg() argument
148 MIRBuilder.buildMerge(ValVReg, {Lo, Hi}); in assignValueToReg()
152 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
160 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
164 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
190 void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg, in assignValueToAddress() argument
196 MIRBuilder.buildTrunc(ValVReg, Load); in assignValueToAddress()
198 buildLoad(ValVReg, VA); in assignValueToAddress()
[all …]
DMipsCallLowering.h52 virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA,
55 virtual void assignValueToAddress(Register ValVReg,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp96 void assignValueToReg(Register ValVReg, const CCValAssign &VA,
102 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
136 void IncomingValueHandler::assignValueToReg(Register ValVReg, in assignValueToReg() argument
149 .addDef(ValVReg) in assignValueToReg()
158 .addDef(ValVReg) in assignValueToReg()
169 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
173 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
201 void IncomingValueHandler::assignValueToAddress(Register ValVReg, in assignValueToAddress() argument
208 MIRBuilder.buildTrunc(ValVReg, LoadReg); in assignValueToAddress()
210 buildLoad(ValVReg, VA); in assignValueToAddress()
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DMipsCallLowering.h51 virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA,
54 virtual void assignValueToAddress(Register ValVReg,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp124 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
141 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg); in assignValueToReg()
144 ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
149 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
151 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
249 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
254 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); in assignValueToAddress()
257 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
275 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
279 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
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/external/llvm-project/llvm/lib/Target/X86/
DX86CallLowering.cpp121 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
140 MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg).getReg(0); in assignValueToReg()
142 ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
147 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
150 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
246 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
252 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); in assignValueToAddress()
255 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
273 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
277 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
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/external/llvm-project/llvm/lib/Target/ARM/
DARMCallLowering.cpp111 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
119 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
124 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
129 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
304 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
314 assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm"); in assignValueToAddress()
317 MIRBuilder.buildTrunc(ValVReg, LoadVReg); in assignValueToAddress()
320 buildLoad(ValVReg, Addr, Size, MPO); in assignValueToAddress()
333 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
346 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp115 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
123 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
128 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
133 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
309 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
319 assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm"); in assignValueToAddress()
323 MIRBuilder.buildTrunc(ValVReg, LoadVReg); in assignValueToAddress()
326 buildLoad(ValVReg, Addr, Size, /* Alignment */ 1, MPO); in assignValueToAddress()
337 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
350 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp44 Register extendRegisterMin32(Register ValVReg, CCValAssign &VA) { in extendRegisterMin32()
48 return MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in extendRegisterMin32()
51 return extendRegister(ValVReg, VA); in extendRegisterMin32()
67 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
72 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
74 Register ExtReg = extendRegisterMin32(ValVReg, VA); in assignValueToReg()
119 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
127 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
136 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
140 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
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/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp70 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
75 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
81 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
87 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize, in assignValueToAddress()
92 const LLT RegTy = MRI.getType(ValVReg); in assignValueToAddress()
98 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); in assignValueToAddress()
166 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
169 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
173 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
178 MIRBuilder.buildStore(ValVReg, Addr, *MMO); in assignValueToAddress()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp47 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
52 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
58 ExtReg = MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in assignValueToReg()
60 ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
94 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
102 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
111 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
115 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
120 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
125 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); in assignValueToAddress()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp71 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
76 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
82 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
88 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
94 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); in assignValueToAddress()
169 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
172 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
176 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
180 ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(Size * 8), ValVReg) in assignValueToAddress()
186 MIRBuilder.buildStore(ValVReg, Addr, *MMO); in assignValueToAddress()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DCallLowering.h134 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
140 virtual void assignValueToAddress(Register ValVReg, Register Addr,
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DCallLowering.h137 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
143 virtual void assignValueToAddress(Register ValVReg, Register Addr,