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Searched refs:ValueVT (Results 1 – 19 of 19) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp321 EVT ValueVT = LD->getValueType(0); in SelectIndexedLoad() local
322 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
326 ValueVT = MVT::i32; in SelectIndexedLoad()
330 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in SelectIndexedLoad()
342 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in SelectIndexedLoad()
543 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
588 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
999 EVT ValueVT = N->getValueType(0); in SelectBitOp() local
1002 if (!(ValueVT == MVT::i32 || ValueVT == MVT::i64 || in SelectBitOp()
1003 ValueVT == MVT::f32 || ValueVT == MVT::f64)) { in SelectBitOp()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp121 MVT PartVT, EVT ValueVT, const Value *V);
130 MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
132 if (ValueVT.isVector()) in getCopyFromParts()
134 PartVT, ValueVT, V); in getCopyFromParts()
142 if (ValueVT.isInteger()) { in getCopyFromParts()
144 unsigned ValueBits = ValueVT.getSizeInBits(); in getCopyFromParts()
151 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
193 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
198 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in getCopyFromParts()
200 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
[all …]
DLegalizeTypesGeneric.cpp261 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
262 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
292 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
476 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
477 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
491 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
DFunctionLoweringInfo.cpp384 EVT ValueVT = ValueVTs[Value]; in CreateRegs() local
385 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
387 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp196 MVT PartVT, EVT ValueVT, const Value *V,
206 MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
209 if (ValueVT.isVector()) in getCopyFromParts()
210 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
219 if (ValueVT.isInteger()) { in getCopyFromParts()
221 unsigned ValueBits = ValueVT.getSizeInBits(); in getCopyFromParts()
228 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
270 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
275 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in getCopyFromParts()
277 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
[all …]
DLegalizeTypesGeneric.cpp250 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
251 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
276 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
461 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
462 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
474 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
DFunctionLoweringInfo.cpp377 EVT ValueVT = ValueVTs[Value]; in CreateRegs() local
378 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
380 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
DLegalizeVectorTypes.cpp4537 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE() local
4539 ValueVT.getVectorElementType(), in WidenVecOp_MSTORE()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp156 MVT PartVT, EVT ValueVT, const Value *V,
166 MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
172 PartVT, ValueVT, CC)) in getCopyFromParts()
175 if (ValueVT.isVector()) in getCopyFromParts()
176 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
184 if (ValueVT.isInteger()) { in getCopyFromParts()
186 unsigned ValueBits = ValueVT.getSizeInBits(); in getCopyFromParts()
193 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
235 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
240 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in getCopyFromParts()
[all …]
DLegalizeTypesGeneric.cpp256 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
257 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
281 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
466 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
467 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
478 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
DFunctionLoweringInfo.cpp388 EVT ValueVT = ValueVTs[Value]; in CreateRegs() local
389 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
391 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
DLegalizeVectorTypes.cpp4698 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE() local
4700 ValueVT.getVectorElementType(), in WidenVecOp_MSTORE()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp149 EVT ValueVT = LD->getValueType(0); in SelectIndexedLoad() local
150 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
154 ValueVT = MVT::i32; in SelectIndexedLoad()
158 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in SelectIndexedLoad()
170 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in SelectIndexedLoad()
472 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
519 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp149 EVT ValueVT = LD->getValueType(0); in SelectIndexedLoad() local
150 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
154 ValueVT = MVT::i32; in SelectIndexedLoad()
158 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in SelectIndexedLoad()
170 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in SelectIndexedLoad()
472 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
519 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1361 EVT ValueVT = Value.getValueType(); in LowerSTORE() local
1364 ValueVT.isVector()) { in LowerSTORE()
1407 ValueVT.bitsGE(MVT::i32)) { in LowerSTORE()
1436 if (ValueVT.isVector()) { in LowerSTORE()
1437 unsigned NumElemVT = ValueVT.getVectorNumElements(); in LowerSTORE()
1438 EVT ElemVT = ValueVT.getVectorElementType(); in LowerSTORE()
1458 if (ValueVT == MVT::i8) { in LowerSTORE()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp5634 MVT ValueVT = Node->getSimpleValueType(0); in Select() local
5640 if (!ValueVT.isVector() || !MaskVT.isVector()) in Select()
5643 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
5644 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
5677 assert(EVT(MaskVT) == EVT(ValueVT).changeVectorElementTypeToInteger() && in Select()
5708 SDVTList VTs = CurDAG->getVTList(ValueVT, MaskVT, MVT::Other); in Select()
5731 MVT ValueVT = Value.getSimpleValueType(); in Select() local
5736 if (!ValueVT.isVector()) in Select()
5739 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
5740 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.h836 MVT PartVT, EVT ValueVT,
DARMISelLowering.cpp4214 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
4215 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in splitValueIntoRegisterParts()
4217 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
4230 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4232 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in joinRegisterPartsIntoValue()
4234 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
4240 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
/external/llvm-project/llvm/include/llvm/CodeGen/
DTargetLowering.h3664 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument