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Searched refs:VectorFormat (Results 1 – 9 of 9) sorted by relevance

/external/vixl/src/aarch64/
Dsimulator-aarch64.h412 void SetActive(VectorFormat vform, int lane_index, bool value) { in SetActive()
421 bool IsActive(VectorFormat vform, int lane_index) const { in IsActive()
512 int64_t Int(VectorFormat vform, int index) const { in Int()
535 uint64_t Uint(VectorFormat vform, int index) const { in Uint()
558 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified()
562 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified()
569 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt()
590 void SetIntArray(VectorFormat vform, const int64_t* src) const { in SetIntArray()
597 void SetUint(VectorFormat vform, int index, uint64_t value) const { in SetUint()
618 void SetUintArray(VectorFormat vform, const uint64_t* src) const { in SetUintArray()
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Dlogic-aarch64.cc170 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1()
179 void Simulator::ld1(VectorFormat vform, in ld1()
187 void Simulator::ld1r(VectorFormat vform, in ld1r()
188 VectorFormat unpack_vform, in ld1r()
204 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r()
209 void Simulator::ld2(VectorFormat vform, in ld2()
226 void Simulator::ld2(VectorFormat vform, in ld2()
239 void Simulator::ld2r(VectorFormat vform, in ld2r()
253 void Simulator::ld3(VectorFormat vform, in ld3()
275 void Simulator::ld3(VectorFormat vform, in ld3()
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Dinstructions-aarch64.h179 enum VectorFormat { enum
303 VectorFormat GetSVEVectorFormat() const { in GetSVEVectorFormat()
682 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
683 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
684 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
685 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
686 VectorFormat ScalarFormatFromLaneSize(int lane_size_in_bits);
687 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
688 VectorFormat VectorFormatFillQ(VectorFormat vform);
689 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
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Dinstructions-aarch64.cc55 VectorFormat movprfx_vform = in CanTakeSVEMovprfx()
90 VectorFormat instr_vform = in CanTakeSVEMovprfx()
255 VectorFormat instr_vform = in CanTakeSVEMovprfx()
396 VectorFormat instr_vform = in CanTakeSVEMovprfx()
1008 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth()
1036 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth()
1059 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ()
1083 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) { in VectorFormatHalfWidthDoubleLanes()
1109 VectorFormat VectorFormatDoubleLanes(VectorFormat vform) { in VectorFormatDoubleLanes()
1125 VectorFormat VectorFormatHalfLanes(VectorFormat vform) { in VectorFormatHalfLanes()
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Dsimulator-aarch64.cc374 void Simulator::ExtractFromSimVRegister(VectorFormat vform, in ExtractFromSimVRegister()
674 VectorFormat vform) { in GetPrintRegisterFormat()
718 VectorFormat vform) { in GetPrintRegisterFormatFP()
4087 VectorFormat vform; in VisitFPDataProcessing1Source()
4233 VectorFormat vform; in VisitFPDataProcessing2Source()
4674 VectorFormat vf = nfd.GetVectorFormat(); in VisitNEON2RegMisc()
4678 VectorFormat vf_lp = nfd.GetVectorFormat(&map_lp); in VisitNEON2RegMisc()
4681 VectorFormat vf_fcvtl = nfd.GetVectorFormat(&map_fcvtl); in VisitNEON2RegMisc()
4685 VectorFormat vf_fcvtn = nfd.GetVectorFormat(&map_fcvtn); in VisitNEON2RegMisc()
4772 VectorFormat fpf = nfd.GetVectorFormat(nfd.FPFormatMap()); in VisitNEON2RegMisc()
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Dregisters-aarch64.h559 VRegister(int code, VectorFormat format) in VRegister()
602 ZRegister(int code, VectorFormat format) in ZRegister()
687 PRegisterWithLaneSize(int code, VectorFormat format) in PRegisterWithLaneSize()
Dassembler-aarch64.cc4520 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
4523 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
4566 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
4607 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in umov()
4643 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in smov()
Dassembler-aarch64.h6474 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format)); in ImmNEON5()
6481 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format)); in ImmNEON4()
/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc1442 VectorFormat vd_form, in Test1OpNEON_Helper()
1443 VectorFormat vn_form, in Test1OpNEON_Helper()
1536 VectorFormat vd_form, in Test1OpNEON()
1537 VectorFormat vn_form) { in Test1OpNEON()
1650 VectorFormat vd_form, in Test1OpAcrossNEON_Helper()
1651 VectorFormat vn_form, in Test1OpAcrossNEON_Helper()
1744 VectorFormat vd_form, in Test1OpAcrossNEON()
1745 VectorFormat vn_form) { in Test1OpAcrossNEON()
1878 VectorFormat vd_form, in Test2OpNEON_Helper()
1879 VectorFormat vn_form, in Test2OpNEON_Helper()
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