Searched refs:WriteLane (Results 1 – 4 of 4) sorted by relevance
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAtomicOptimizer.cpp | 350 Function *WriteLane = in buildShiftRight() local
367 V = B.CreateCall(WriteLane, {B.CreateCall(ReadLane, {Old, B.getInt32(15)}), in buildShiftRight()
373 WriteLane, in buildShiftRight()
378 WriteLane, in buildShiftRight()
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| D | SIRegisterInfo.cpp | 1151 MachineInstrBuilder WriteLane = in spillSGPR() local
1165 WriteLane.addReg(SuperReg, RegState::Implicit | SuperKillState); in spillSGPR()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAtomicOptimizer.cpp | 350 Function *WriteLane = in buildShiftRight() local
367 V = B.CreateCall(WriteLane, {B.CreateCall(ReadLane, {Old, B.getInt32(15)}), in buildShiftRight()
373 WriteLane, in buildShiftRight()
378 WriteLane, in buildShiftRight()
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| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 276 WriteLane(new_value, 0); in Write()
295 WriteLane(new_value, lane); in Insert()
355 void WriteLane(T src, int lane) { in WriteLane() function
371 void WriteLane(vixl::internal::SimFloat16 src, int lane) { in WriteLane() function
372 WriteLane(Float16ToRawbits(src), lane); in WriteLane()
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