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Searched refs:WriteMask (Results 1 – 25 of 115) sorted by relevance

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/external/mesa3d/src/gallium/drivers/i915/
Di915_fpc_optimize.c234 o->WriteMask = i->WriteMask; in copy_dst_reg()
457 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_X) in i915_fpc_optimize_mov_after_mov()
459 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_Y) in i915_fpc_optimize_mov_after_mov()
461 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_Z) in i915_fpc_optimize_mov_after_mov()
463 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_W) in i915_fpc_optimize_mov_after_mov()
466 dst_reg2->Register.WriteMask |= dst_reg1->Register.WriteMask; in i915_fpc_optimize_mov_after_mov()
496 …unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) && in i915_fpc_optimize_mov_after_alu()
497 …unswizzled(&current->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) && in i915_fpc_optimize_mov_after_alu()
498 … is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) ) in i915_fpc_optimize_mov_after_alu()
504 next->FullInstruction.Dst[0].Register.WriteMask, in i915_fpc_optimize_mov_after_alu()
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/external/mesa3d/src/mesa/program/
Dprog_instruction.c56 inst[i].DstReg.WriteMask = WRITEMASK_XYZW; in _mesa_init_instructions()
212 if (inst->DstReg.WriteMask == WRITEMASK_X || in _mesa_check_soa_dependencies()
213 inst->DstReg.WriteMask == WRITEMASK_Y || in _mesa_check_soa_dependencies()
214 inst->DstReg.WriteMask == WRITEMASK_Z || in _mesa_check_soa_dependencies()
215 inst->DstReg.WriteMask == WRITEMASK_W || in _mesa_check_soa_dependencies()
216 inst->DstReg.WriteMask == 0x0) { in _mesa_check_soa_dependencies()
228 if (inst->DstReg.WriteMask & (1 << chan)) { in _mesa_check_soa_dependencies()
Dprog_optimize.c79 channel_mask = inst->DstReg.WriteMask & dst_mask; in get_src_arg_mask()
123 const GLuint mask = mov->DstReg.WriteMask; in get_dst_mask_for_mov()
309 inst->DstReg.WriteMask & (1 << chan)) { in _mesa_remove_dead_code_global()
314 inst->DstReg.WriteMask &= ~(1 << chan); in _mesa_remove_dead_code_global()
319 if (inst->DstReg.WriteMask == 0) { in _mesa_remove_dead_code_global()
398 mask &= ~inst->DstReg.WriteMask; in find_next_use()
494 dst_mask = mov->DstReg.WriteMask; in _mesa_remove_extra_move_use()
543 dst_mask &= ~inst2->DstReg.WriteMask; in _mesa_remove_extra_move_use()
551 src_mask &= ~inst2->DstReg.WriteMask; in _mesa_remove_extra_move_use()
583 const GLuint mask = inst->DstReg.WriteMask; in _mesa_remove_dead_code_local()
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Dprogramopt.c92 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i); in insert_mvp_dp4_code()
163 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
175 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
190 newInst[3].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
321 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
342 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
356 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
369 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
381 inst->DstReg.WriteMask = WRITEMASK_XYZ; in _mesa_append_fog_code()
396 inst->DstReg.WriteMask = WRITEMASK_W; in _mesa_append_fog_code()
/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_pair_translate.c90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0; in classify_instruction()
91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0; in classify_instruction()
275 inst->DstReg.WriteMask); in set_pair_instruction()
286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
293 inst->DstReg.WriteMask & RC_MASK_XYZ; in set_pair_instruction()
295 GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
303 pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ; in set_pair_instruction()
307 pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask, 3) << 3); in set_pair_instruction()
308 if (pair->Alpha.WriteMask) { in set_pair_instruction()
Dradeon_program_tex.c92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; in projective_divide()
173 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in radeonTransformTEX()
183 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX()
194 inst_mul->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX()
210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX()
311 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
333 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
342 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
353 inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
368 inst_add->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
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Dradeon_dataflow_deadcode.c41 unsigned char WriteMask:4; member
162 usedmask = *pused & inst->U.I.DstReg.WriteMask; in update_instruction()
167 insts->WriteMask |= usedmask; in update_instruction()
257 ptr->U.I.DstReg.WriteMask, srcmasks); in rc_dataflow_deadcode()
324 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask; in rc_dataflow_deadcode()
325 if (s.Instructions[ip].WriteMask) in rc_dataflow_deadcode()
341 usemask = s.Instructions[ip].WriteMask; in rc_dataflow_deadcode()
Dradeon_variable.c61 if (var_ptr->Dst.WriteMask == RC_MASK_W) { in rc_variable_change_dst()
157 unsigned int mask = var->Readers[i].WriteMask; in rc_variable_compute_live_intervals()
286 new->Dst.WriteMask = DstWriteMask; in rc_variable()
333 if (sub_inst->WriteMask) { in get_variable_pair_helper()
335 writemask = sub_inst->WriteMask; in get_variable_pair_helper()
374 inst->U.I.DstReg.WriteMask, &reader_data); in rc_get_variables()
395 writemask |= var->Dst.WriteMask; in rc_variable_writemask_sum()
526 var->Inst->IP, var->Dst.Index, var->Dst.WriteMask); in rc_variable_print()
Dr3xx_fragprog.c64 if (inst->DstReg.WriteMask & RC_MASK_Z) { in rc_rewrite_depth_out()
65 inst->DstReg.WriteMask = RC_MASK_W; in rc_rewrite_depth_out()
67 inst->DstReg.WriteMask = 0; in rc_rewrite_depth_out()
Dradeon_program_alu.c104 dst.WriteMask = mask; in dstregtmpmask()
226 return dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask); in try_to_reuse_dst()
370 if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) { in transform_LIT()
379 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in transform_LIT()
445 tempdst.WriteMask = RC_MASK_W; in transform_POW()
467 unsigned int mask = inst->U.I.DstReg.WriteMask; in transform_ROUND()
600 dstregtmpmask(tmp1, inst->U.I.DstReg.WriteMask), in transform_SSG()
766 dst.WriteMask = RC_MASK_XYZW; in transform_r300_vertex_fix_LIT()
788 dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask), in transform_r300_vertex_SEQ()
815 dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask), in transform_r300_vertex_SNE()
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Dradeon_program_print.c164 if (dst.WriteMask != RC_MASK_XYZW) { in rc_print_dst_register()
166 rc_print_mask(f, dst.WriteMask); in rc_print_dst_register()
389 if (inst->RGB.WriteMask) in rc_print_pair_instruction()
391 (inst->RGB.WriteMask & 1) ? "x" : "", in rc_print_pair_instruction()
392 (inst->RGB.WriteMask & 2) ? "y" : "", in rc_print_pair_instruction()
393 (inst->RGB.WriteMask & 4) ? "z" : ""); in rc_print_pair_instruction()
428 if (inst->Alpha.WriteMask) in rc_print_pair_instruction()
Dradeon_dataflow.c261 if (opcode->HasDstReg && inst->DstReg.WriteMask) in writes_normal()
262 cb(userdata, fullinst, inst->DstReg.File, inst->DstReg.Index, inst->DstReg.WriteMask); in writes_normal()
272 if (inst->RGB.WriteMask) in writes_pair()
273 cb(userdata, fullinst, RC_FILE_TEMPORARY, inst->RGB.DestIndex, inst->RGB.WriteMask); in writes_pair()
275 if (inst->Alpha.WriteMask) in writes_pair()
394 if (inst->RGB.WriteMask) { in remap_pair_instruction()
403 if (inst->Alpha.WriteMask) { in remap_pair_instruction()
486 new->WriteMask = mask; in add_reader()
888 if (sub_writer->WriteMask) { in rc_get_readers_sub()
890 sub_writer->DestIndex, sub_writer->WriteMask); in rc_get_readers_sub()
Dradeon_emulate_branches.c78 inst_mov->U.I.DstReg.WriteMask = RC_MASK_X; in handle_if()
168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in allocate_and_insert_proxies()
187 inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW; in inject_cmp()
298 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in fix_output_writes()
Dradeon_optimize.c458 reader_data->Writer->U.I.DstReg.WriteMask, in presub_scan_read()
583 unsigned dstmask = inst_add->U.I.DstReg.WriteMask; in peephole_add_presub_add()
657 if(((1 << i) & inst_add->U.I.DstReg.WriteMask) in peephole_add_presub_inv()
664 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv()
665 inst_add->U.I.DstReg.WriteMask in peephole_add_presub_inv()
695 d->Writer->File, d->Writer->Index, d->Writer->WriteMask)) { in omod_filter_reader_cb()
710 (mask & d->Writer->WriteMask)) { in omod_filter_writer_cb()
841 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
/external/mesa3d/src/gallium/drivers/r300/compiler/tests/
Drc_test_helpers.c251 struct match_info WriteMask; member
284 tokens.WriteMask.String = dst_str + matches[3].rm_so; in init_rc_normal_dst()
285 tokens.WriteMask.Length = match_length(matches, 3); in init_rc_normal_dst()
310 if (tokens.WriteMask.Length == 0) { in init_rc_normal_dst()
311 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in init_rc_normal_dst()
313 inst->U.I.DstReg.WriteMask = 0; in init_rc_normal_dst()
315 if (tokens.WriteMask.String[0] != '.') { in init_rc_normal_dst()
319 for (i = 1; i < tokens.WriteMask.Length; i++) { in init_rc_normal_dst()
320 switch(tokens.WriteMask.String[i]) { in init_rc_normal_dst()
322 inst->U.I.DstReg.WriteMask |= RC_MASK_X; in init_rc_normal_dst()
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/external/skqp/src/gpu/
DGrUserStencilSettings.h118 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask> struct Init {};
128 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask>
129 constexpr static Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask> StaticInit() { in StaticInit()
130 return Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>(); in StaticInit()
149 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask,
152 const Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>&) in GrUserStencilSettings()
156 Attrs::EffectiveWriteMask(WriteMask)}
160 Attrs::EffectiveWriteMask(WriteMask)} {
/external/skia/src/gpu/
DGrUserStencilSettings.h119 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask> struct Init {};
129 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask>
130 constexpr static Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask> StaticInit() { in StaticInit()
131 return Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>(); in StaticInit()
150 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask,
153 const Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>&) in GrUserStencilSettings()
157 Attrs::EffectiveWriteMask(WriteMask)}
161 Attrs::EffectiveWriteMask(WriteMask)} {
/external/mesa3d/src/mesa/main/
Dstencil.h125 ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[face]); in _mesa_stencil_is_two_sided()
132 (ctx->Stencil.WriteMask[0] != 0 || in _mesa_stencil_is_write_enabled()
134 ctx->Stencil.WriteMask[ctx->Stencil._BackFace] != 0)); in _mesa_stencil_is_write_enabled()
Dstencil.c283 if (ctx->Stencil.WriteMask[face] == mask) in _mesa_StencilMask()
287 ctx->Stencil.WriteMask[face] = mask; in _mesa_StencilMask()
298 if (ctx->Stencil.WriteMask[0] == mask && in _mesa_StencilMask()
299 ctx->Stencil.WriteMask[1] == mask) in _mesa_StencilMask()
303 ctx->Stencil.WriteMask[0] = ctx->Stencil.WriteMask[1] = mask; in _mesa_StencilMask()
581 ctx->Stencil.WriteMask[0] = mask; in stencil_mask_separate()
585 ctx->Stencil.WriteMask[1] = mask; in stencil_mask_separate()
662 ctx->Stencil.WriteMask[0] = 0xFF; in _mesa_init_stencil()
663 ctx->Stencil.WriteMask[1] = 0xFF; in _mesa_init_stencil()
664 ctx->Stencil.WriteMask[2] = 0xFF; in _mesa_init_stencil()
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_lowering.c71 dst->Register.WriteMask &= wrmask; in reg_dst()
72 assert(dst->Register.WriteMask); in reg_dst()
215 if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) { in transform_dst()
227 if (dst->Register.WriteMask & TGSI_WRITEMASK_Z) { in transform_dst()
238 if (dst->Register.WriteMask & TGSI_WRITEMASK_W) { in transform_dst()
249 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) { in transform_dst()
287 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_lrp()
335 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_frc()
381 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_pow()
440 if (dst->Register.WriteMask & TGSI_WRITEMASK_YZ) { in transform_lit()
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Dtgsi_transform.h250 reg->Register.WriteMask = writemask; in tgsi_transform_dst_reg()
302 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op1_inst()
329 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op2_inst()
359 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op3_inst()
387 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op1_swz_inst()
432 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op2_swz_inst()
486 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op3_swz_inst()
Dtgsi_exec.c2346 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_tex()
2390 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) { in exec_lodq()
2394 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) { in exec_lodq()
2407 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_lodq()
2418 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) { in exec_lodq()
2422 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) { in exec_lodq()
2530 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txd()
2607 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txf()
2615 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txf()
2646 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txq()
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/external/mesa3d/src/mesa/state_tracker/
Dst_tgsi_lower_yuv.c66 dst->Register.WriteMask &= wrmask; in reg_dst()
67 assert(dst->Register.WriteMask); in reg_dst()
239 ctx->tmp[i].dst.Register.WriteMask = TGSI_WRITEMASK_XYZW; in emit_decls()
271 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) { in yuv_to_rgb()
280 if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) { in yuv_to_rgb()
289 if (dst->Register.WriteMask & TGSI_WRITEMASK_Z) { in yuv_to_rgb()
298 if (dst->Register.WriteMask & TGSI_WRITEMASK_W) { in yuv_to_rgb()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_shader.c3104 unsigned write_mask = dst->Register.WriteMask; in r600_store_tcs_output()
4464 cf.comp_mask = inst->Dst[0].Register.WriteMask; in tgsi_dst()
4518 unsigned write_mask = inst->Dst[0].Register.WriteMask; in tgsi_op2_64_params()
4613 write_mask = inst->Dst[0].Register.WriteMask; in tgsi_op2_64_params()
4645 unsigned write_mask = inst->Dst[0].Register.WriteMask; in tgsi_op2_64()
4681 if (inst->Dst[0].Register.WriteMask & (1 << i)) in tgsi_op3_64()
4702 unsigned write_mask = inst->Dst[0].Register.WriteMask; in tgsi_op2_s()
4782 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); in tgsi_ineg()
4786 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) in tgsi_ineg()
4813 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); in tgsi_dneg()
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/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_vertprog.c685 dst.WriteMask & WRITEMASK_X) { in r200_translate_vertex_program()
701 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
730 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
747 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
766 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
792 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
815 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
830 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
845 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
864 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
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