| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | patchable-prologue.ll | 3 …fy-machineinstrs -show-mc-encoding -mtriple=i386 < %s | FileCheck %s --check-prefixes=32,32CFI,XCHG
6 …-mc-encoding -mtriple=i386-windows-msvc -mcpu=pentium4 < %s | FileCheck %s --check-prefixes=32,XCHG
25 ; XCHG-NEXT: xchgw %ax, %ax # encoding: [0x66,0x90]
47 ; XCHG-NEXT: xchgw %ax, %ax # encoding: [0x66,0x90]
69 ; XCHG-NEXT: xchgw %ax, %ax # encoding: [0x66,0x90]
93 ; XCHG-NEXT: xchgw %ax, %ax
113 ; XCHG-NEXT: xchgw %ax, %ax
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| /external/strace/xlat/ |
| D | atomic_ops.in | 3 { OR1K_ATOMIC_XCHG, "XCHG" },
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| /external/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| D | MemProfiler.cpp | 356 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in isInterestingMemoryAccess() local
361 DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType()); in isInterestingMemoryAccess()
363 Access.Addr = XCHG->getPointerOperand(); in isInterestingMemoryAccess()
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| D | HWAddressSanitizer.cpp | 666 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in getInterestingMemoryOperands() local
667 if (!ClInstrumentAtomics || ignoreAccess(XCHG->getPointerOperand())) in getInterestingMemoryOperands()
669 Interesting.emplace_back(I, XCHG->getPointerOperandIndex(), true, in getInterestingMemoryOperands()
670 XCHG->getCompareOperand()->getType(), None); in getInterestingMemoryOperands()
689 if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) in getPointerOperandIndex() local
690 return XCHG->getPointerOperandIndex(); in getPointerOperandIndex()
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| D | AddressSanitizer.cpp | 1395 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in getInterestingMemoryOperands() local
1396 if (!ClInstrumentAtomics || ignoreAccess(XCHG->getPointerOperand())) in getInterestingMemoryOperands()
1398 Interesting.emplace_back(I, XCHG->getPointerOperandIndex(), true, in getInterestingMemoryOperands()
1399 XCHG->getCompareOperand()->getType(), None); in getInterestingMemoryOperands()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Instrumentation/ |
| D | HWAddressSanitizer.cpp | 535 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in isInterestingMemoryAccess() local
538 *TypeSize = DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType()); in isInterestingMemoryAccess()
540 PtrOperand = XCHG->getPointerOperand(); in isInterestingMemoryAccess()
568 if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) in getPointerOperandIndex() local
569 return XCHG->getPointerOperandIndex(); in getPointerOperandIndex()
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| D | AddressSanitizer.cpp | 1376 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in isInterestingMemoryAccess() local
1379 *TypeSize = DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType()); in isInterestingMemoryAccess()
1381 PtrOperand = XCHG->getPointerOperand(); in isInterestingMemoryAccess()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver2.td | 514 // XCHG.
520 def : InstRW<[Zn2WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
527 def : InstRW<[Zn2WriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86ScheduleZnver1.td | 532 // XCHG.
538 def : InstRW<[ZnWriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86ScheduleAtom.td | 583 "XCHG(8|16|32|64)rm",
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| D | X86ScheduleBtVer2.td | 456 // atomic XCHG operations. We need two writes because the instruction latency
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| D | X86SchedBroadwell.td | 1175 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86SchedSkylakeClient.td | 1357 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver2.td | 523 // XCHG.
529 def : InstRW<[Zn2WriteXCHG], (instregex "^XCHG(8|16|32|64)rr", "^XCHG(16|32|64)ar")>;
536 def : InstRW<[Zn2WriteXCHGrm, ReadAfterLd], (instregex "^XCHG(8|16|32|64)rm")>;
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| D | X86ScheduleZnver1.td | 535 // XCHG.
541 def : InstRW<[ZnWriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86ScheduleAtom.td | 586 "XCHG(8|16|32|64)rm",
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| D | X86ScheduleBtVer2.td | 456 // atomic XCHG operations. We need two writes because the instruction latency
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| D | X86SchedBroadwell.td | 1178 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86SchedHaswell.td | 1310 def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86SchedSkylakeClient.td | 1360 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
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| /external/llvm/lib/Target/X86/ |
| D | X86SchedHaswell.td | 447 // XCHG.
454 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
461 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
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| /external/llvm/lib/Transforms/Instrumentation/ |
| D | AddressSanitizer.cpp | 964 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in isInterestingMemoryAccess() local
967 *TypeSize = DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType()); in isInterestingMemoryAccess()
969 PtrOperand = XCHG->getPointerOperand(); in isInterestingMemoryAccess()
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| /external/llvm-project/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 749 class XCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
788 def XCHGD : XCHG<BPF_DW, "64", atomic_swap_64>;
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| /external/llvm-project/llvm/docs/ |
| D | Atomics.rst | 437 generate an ``XCHG``, other stores generate a ``MOV``. SequentiallyConsistent
440 uses ``XCHG``, ``atomicrmw add`` and ``atomicrmw sub`` use ``XADD``, and all
|
| /external/llvm/docs/ |
| D | Atomics.rst | 435 generate an ``XCHG``, other stores generate a ``MOV``. SequentiallyConsistent
438 uses ``XCHG``, ``atomicrmw add`` and ``atomicrmw sub`` use ``XADD``, and all
|