| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 444 ZERO_EXTEND_VECTOR_INREG, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 580 ZERO_EXTEND_VECTOR_INREG, enumerator
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 729 ZERO_EXTEND_VECTOR_INREG, enumerator
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| /external/llvm-project/llvm/unittests/CodeGen/ |
| D | AArch64SelectionDAGTest.cpp | 96 auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
111 auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 330 case ISD::ZERO_EXTEND_VECTOR_INREG: in LegalizeOp()
685 case ISD::ZERO_EXTEND_VECTOR_INREG: in Expand()
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| D | SelectionDAGDumper.cpp | 247 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 623 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorResult()
2131 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVectorResult()
2443 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
2461 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
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| D | LegalizeIntegerTypes.cpp | 107 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
3360 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 68 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
396 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
861 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorResult()
1980 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorOperand()
2787 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVectorResult()
3255 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
3363 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
3381 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4319 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
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| D | SelectionDAGDumper.cpp | 325 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 441 case ISD::ZERO_EXTEND_VECTOR_INREG: in LegalizeOp()
857 case ISD::ZERO_EXTEND_VECTOR_INREG: in Expand()
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| D | TargetLowering.cpp | 1678 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
1683 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
1752 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; in SimplifyDemandedBits()
2514 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyDemandedVectorElts()
2532 if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { in SimplifyDemandedVectorElts()
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| D | LegalizeIntegerTypes.cpp | 112 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
4357 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 69 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
406 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
920 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorResult()
2113 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorOperand()
2945 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVectorResult()
3422 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
3526 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
3544 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4486 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
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| D | LegalizeVectorOps.cpp | 438 case ISD::ZERO_EXTEND_VECTOR_INREG: in LegalizeOp()
738 case ISD::ZERO_EXTEND_VECTOR_INREG: in Expand()
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| D | SelectionDAGDumper.cpp | 335 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg"; in getOperationName()
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| D | TargetLowering.cpp | 790 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyMultipleUseDemandedBits()
1849 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
1854 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
1928 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; in SimplifyDemandedBits()
2748 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyDemandedVectorElts()
2766 if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { in SimplifyDemandedVectorElts()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 85 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
140 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
1437 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(Op), ty(Op), in LowerHvxExtend()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 101 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
164 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
1634 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(Op), ty(Op), in LowerHvxExtend()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 699 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 900 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 817 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 323 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
4579 case ISD::ZERO_EXTEND_VECTOR_INREG: in LowerOperation()
4779 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG || in combineExtract()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 374 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
5199 case ISD::ZERO_EXTEND_VECTOR_INREG: in LowerOperation()
5511 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG || in combineExtract()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 408 def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>;
|