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Searched refs:_reg_nr (Results 1 – 4 of 4) sorted by relevance

/external/igt-gpu-tools/assembler/
Dgen8_disasm.c335 reg(FILE *file, unsigned reg_file, unsigned _reg_nr) in reg() argument
340 switch (_reg_nr & 0xf0) { in reg()
345 format(file, "a%d", _reg_nr & 0x0f); in reg()
348 format(file, "acc%d", _reg_nr & 0x0f); in reg()
351 format(file, "f%d", _reg_nr & 0x0f); in reg()
354 format(file, "mask%d", _reg_nr & 0x0f); in reg()
357 format(file, "msd%d", _reg_nr & 0x0f); in reg()
360 format(file, "sr%d", _reg_nr & 0x0f); in reg()
363 format(file, "cr%d", _reg_nr & 0x0f); in reg()
366 format(file, "n%d", _reg_nr & 0x0f); in reg()
[all …]
Dbrw_disasm.c461 static int reg (FILE *file, unsigned _reg_file, unsigned _reg_nr) in reg() argument
467 _reg_nr &= ~(1 << 7); in reg()
470 switch (_reg_nr & 0xf0) { in reg()
475 format (file, "a%d", _reg_nr & 0x0f); in reg()
478 format (file, "acc%d", _reg_nr & 0x0f); in reg()
481 format (file, "f%d", _reg_nr & 0x0f); in reg()
484 format (file, "mask%d", _reg_nr & 0x0f); in reg()
487 format (file, "msd%d", _reg_nr & 0x0f); in reg()
490 format (file, "sr%d", _reg_nr & 0x0f); in reg()
493 format (file, "cr%d", _reg_nr & 0x0f); in reg()
[all …]
/external/mesa3d/src/intel/compiler/
Dbrw_disasm.c687 reg(FILE *file, unsigned _reg_file, unsigned _reg_nr) in reg() argument
693 _reg_nr &= ~BRW_MRF_COMPR4; in reg()
696 switch (_reg_nr & 0xf0) { in reg()
701 format(file, "a%d", _reg_nr & 0x0f); in reg()
704 format(file, "acc%d", _reg_nr & 0x0f); in reg()
707 format(file, "f%d", _reg_nr & 0x0f); in reg()
710 format(file, "mask%d", _reg_nr & 0x0f); in reg()
713 format(file, "ms%d", _reg_nr & 0x0f); in reg()
716 format(file, "msd%d", _reg_nr & 0x0f); in reg()
719 format(file, "sr%d", _reg_nr & 0x0f); in reg()
[all …]
Dbrw_eu_compact.c1692 brw_compact_inst_set_##field##_reg_nr(devinfo, &temp, \ in try_compact_instruction()
2049 brw_compact_inst_##field##_reg_nr(devinfo, src)) in uncompact_instruction()