Home
last modified time | relevance | path

Searched refs:a53 (Results 1 – 25 of 147) sorted by relevance

123456

/external/arm-trusted-firmware/plat/amlogic/gxbb/
Dplatform.mk41 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
43 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
45 TF_CFLAGS_aarch64 += -mtune=cortex-a53
/external/arm-trusted-firmware/plat/amlogic/axg/
Dplatform.mk45 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
47 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
49 TF_CFLAGS_aarch64 += -mtune=cortex-a53
/external/arm-trusted-firmware/plat/amlogic/gxl/
Dplatform.mk45 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
47 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
49 TF_CFLAGS_aarch64 += -mtune=cortex-a53
/external/arm-trusted-firmware/plat/amlogic/g12a/
Dplatform.mk45 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
47 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
49 TF_CFLAGS_aarch64 += -mtune=cortex-a53
/external/llvm/test/CodeGen/AArch64/
Dpostra-mi-sched.ll1 ; RUN: llc < %s -O3 -march=aarch64 -mcpu=cortex-a53 | FileCheck %s
3 ; With cortex-a53, each of fmul and fcvt have latency of 6 cycles. After the
Daarch64-fix-cortex-a53-835769.ll5 ; cases could break if instruction scheduling heuristics for cortex-a53 change
6 ; RUN: llc < %s -mcpu=cortex-a53 -aarch64-fix-cortex-a53-835769=1 -stats 2>&1 \
8 ; RUN: llc < %s -mcpu=cortex-a53 -aarch64-fix-cortex-a53-835769=0 -stats 2>&1 \
16 ; RUN: llc < %s -mcpu=cortex-a53 | FileCheck %s --check-prefix CHECK-BASIC-PASS-DISABLED
534 ; CHECK: 11 aarch64-fix-cortex-a53-835769 - Number of Nops added to work around erratum 835769
Darm64-misched-forwarding-A53.ll2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -ver…
Dcpus.ll6 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
Dremat.ll3 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
Darm64-triv-disjoint-mem-access.ll1 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -enable-aa-sched-mi | FileCheck %s
Darm64-misched-basic-A53.ll2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -ver…
3 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -ver…
115 ; [ARM64] Cortex-a53 schedule mode can't handle NEON post-increment load
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dpostra-mi-sched.ll1 ; RUN: llc < %s -O3 -mtriple=aarch64-eabi -mcpu=cortex-a53 | FileCheck %s
3 ; With cortex-a53, each of fmul and fcvt have latency of 6 cycles. After the
Daarch64-fix-cortex-a53-835769.ll5 ; cases could break if instruction scheduling heuristics for cortex-a53 change
6 ; RUN: llc < %s -mcpu=cortex-a53 -aarch64-fix-cortex-a53-835769=1 -frame-pointer=non-leaf -stats 2>…
8 ; RUN: llc < %s -mcpu=cortex-a53 -aarch64-fix-cortex-a53-835769=0 -frame-pointer=non-leaf -stats 2>…
16 ; RUN: llc < %s -mcpu=cortex-a53 -frame-pointer=non-leaf | FileCheck %s --check-prefix CHECK-BASIC-…
534 ; CHECK: 11 aarch64-fix-cortex-a53-835769 - Number of Nops added to work around erratum 835769
Darm64-misched-forwarding-A53.ll2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -ver…
Darm64-triv-disjoint-mem-access.ll1 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -enable-aa-sched-mi | FileCheck %s
Darm64-misched-basic-A53.ll2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -ver…
3 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -ver…
115 ; [ARM64] Cortex-a53 schedule mode can't handle NEON post-increment load
Daarch64-DAGCombine-findBetterNeighborChains-crash.ll42 attributes #1 = { nounwind "target-cpu"="cortex-a53" }
/external/arm-trusted-firmware/plat/rpi/rpi3/
Dplatform.mk55 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
57 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
59 TF_CFLAGS_aarch64 += -mtune=cortex-a53
/external/arm-trusted-firmware/lib/cpus/
Dcpu-ops.mk666 TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419
670 TF_CFLAGS_aarch64 += -mfix-cortex-a53-835769
671 TF_LDFLAGS_aarch64 += --fix-cortex-a53-835769
/external/XNNPACK/scripts/
Dgenerate-f32-gemm.sh49 …/f32-gemm/1x12-aarch64-neonfma-cortex-a53.S.in -D INC=0 -o src/f32-gemm/gen/1x12-minmax-aarch64-ne…
50 …2-gemm/1x12-aarch64-neonfma-cortex-a53.S.in -D INC=1 -o src/f32-gemm/gen-inc/1x12inc-minmax-aarch6…
52 …c/f32-gemm/1x8-aarch64-neonfma-cortex-a53.S.in -D INC=0 -o src/f32-gemm/gen/1x8-minmax-aarch64-ne…
53 …32-gemm/1x8-aarch64-neonfma-cortex-a53.S.in -D INC=1 -o src/f32-gemm/gen-inc/1x8inc-minmax-aarch6…
61 …/f32-gemm/4x12-aarch64-neonfma-cortex-a53.S.in -D INC=0 -o src/f32-gemm/gen/4x12-minmax-aarch64-ne…
62 …2-gemm/4x12-aarch64-neonfma-cortex-a53.S.in -D INC=1 -o src/f32-gemm/gen-inc/4x12inc-minmax-aarch6…
64 …c/f32-gemm/4x8-aarch64-neonfma-cortex-a53.S.in -D INC=0 -o src/f32-gemm/gen/4x8-minmax-aarch64-ne…
65 …32-gemm/4x8-aarch64-neonfma-cortex-a53.S.in -D INC=1 -o src/f32-gemm/gen-inc/4x8inc-minmax-aarch6…
91 …c/f32-gemm/6x8-aarch64-neonfma-cortex-a53.S.in -D INC=0 -o src/f32-gemm/gen/6x8-minmax-aarch64-ne…
92 …32-gemm/6x8-aarch64-neonfma-cortex-a53.S.in -D INC=1 -o src/f32-gemm/gen-inc/6x8inc-minmax-aarch6…
/external/llvm-project/llvm/test/CodeGen/ARM/
Dlsr-scale-addr-mode.ll4 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
Drelax-per-target-feature.ll31 attributes #0 = { nounwind "disable-tail-calls"="false" "target-cpu"="cortex-a53" "target-features…
/external/llvm-project/llvm/test/Transforms/CorrelatedValuePropagation/
Dcrash.ll118 %a53 = and i1 %a52, %a52
119 %a54 = and i1 %a53, %a53
/external/pigweed/pw_preprocessor/public/pw_preprocessor/
Darguments.h178 a56, a55, a54, a53, a52, a51, a50, a49, \ argument
/external/cpuinfo/test/build.prop/
Dnexus5x.log134 dalvik.vm.isa.arm64.variant=cortex-a53
136 dalvik.vm.isa.arm.variant=cortex-a53.a57

123456