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/external/llvm-project/llvm/test/CodeGen/AArch64/
Dloh.mir1 # RUN: llc -o /dev/null %s -mtriple=aarch64-apple-ios -run-pass=aarch64-collect-loh -debug-only=aar…
2 …nd-strip-all-safe -o /dev/null %s -mtriple=aarch64-apple-ios -run-pass=aarch64-collect-loh -debug-…
26 ; CHECK-NEXT: $x1 = ADRP target-flags(aarch64-page) @g3
27 ; CHECK-NEXT: $x1 = ADRP target-flags(aarch64-page) @g4
29 ; CHECK-NEXT: $x1 = ADRP target-flags(aarch64-page) @g2
30 ; CHECK-NEXT: $x1 = ADRP target-flags(aarch64-page) @g3
32 ; CHECK-NEXT: $x0 = ADRP target-flags(aarch64-page) @g0
33 ; CHECK-NEXT: $x0 = ADRP target-flags(aarch64-page) @g1
34 $x0 = ADRP target-flags(aarch64-page) @g0
35 $x0 = ADRP target-flags(aarch64-page) @g1
[all …]
Dmisched-fusion-aes.ll1 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-aes,+crypto | FileCheck %s
2 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto | FileCheck %s
3 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s
4 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s
5 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s
6 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s
7 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s
8 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s
9 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s
11 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k)
[all …]
Dmachine-outliner-retaddr-sign-sp-mod.mir5 target triple = "aarch64-arm-linux-gnu"
73 renamable $x8 = ADRP target-flags(aarch64-page) @v
75 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
76 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
77 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
78 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
79 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
80 …STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile sto…
81 …STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v ::…
106 renamable $x8 = ADRP target-flags(aarch64-page) @v
[all …]
Dremat.ll1 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a34 -o - %s | FileCheck %s
2 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s | FileCheck %s
3 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
4 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a55 -o - %s | FileCheck %s
5 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
6 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a65 -o - %s | FileCheck %s
7 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a65ae -o - %s | FileCheck %s
8 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
9 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s | FileCheck %s
10 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a75 -o - %s | FileCheck %s
[all …]
Darm64-cvt.ll1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)
18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)
34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)
38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone
39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone
40 declare i32 @llvm.aarch64.neon.fcvtas.i32.f64(double) nounwind readnone
41 declare i64 @llvm.aarch64.neon.fcvtas.i64.f64(double) nounwind readnone
50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
[all …]
Darm64-neon-across.ll3 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
5 declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)
7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
9 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
11 declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)
13 declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)
15 declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)
17 declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)
19 declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>)
[all …]
Dsve-intrinsic-opts-ptest.ll1 ; RUN: opt -S -aarch64-sve-intrinsic-opts -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCh…
9 ; OPT: %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 0)
11 ; OPT-NEXT: %[[OUT:.*]] = call i1 @llvm.aarch64.sve.ptest.any.nxv2i1(<vscale x 2 x i1> %mask, <vsca…
13 %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 0)
14 …%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %ma…
15 %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %a)
16 %out = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
23 ; OPT: %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
24 ; OPT-NEXT: %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x …
25 ; OPT-NEXT: %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x …
[all …]
Dpreferred-function-alignment.ll1 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=generic < %s | FileCheck --check-prefixes=ALIGN2,CH…
2 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a35 < %s | FileCheck --check-prefixes=ALIGN2…
3 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a53 < %s | FileCheck --check-prefixes=ALIGN3…
4 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 < %s | FileCheck --check-prefixes=ALIGN4…
5 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a65 < %s | FileCheck --check-prefixes=ALIGN3…
6 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a65ae < %s | FileCheck --check-prefixes=ALIG…
7 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a72 < %s | FileCheck --check-prefixes=ALIGN4…
8 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a73 < %s | FileCheck --check-prefixes=ALIGN4…
9 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a75 < %s | FileCheck --check-prefixes=ALIGN4…
10 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a76 < %s | FileCheck --check-prefixes=ALIGN4…
[all …]
Dsettag-merge.ll1 ; RUN: llc < %s -mtriple=aarch64 -mattr=+mte -aarch64-order-frame-objects=0 | FileCheck %s
4 declare void @llvm.aarch64.settag(i8* %p, i64 %a)
5 declare void @llvm.aarch64.settag.zero(i8* %p, i64 %a)
14 call void @llvm.aarch64.settag(i8* %a, i64 16)
15 call void @llvm.aarch64.settag(i8* %b, i64 16)
30 call void @llvm.aarch64.settag(i8* %a, i64 16)
31 call void @llvm.aarch64.settag(i8* %b, i64 16)
32 call void @llvm.aarch64.settag(i8* %c, i64 16)
33 call void @llvm.aarch64.settag(i8* %d, i64 16)
47 call void @llvm.aarch64.settag(i8* %a, i64 16)
[all …]
Darm64-fminv.ll6 %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in)
13 %min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in)
20 %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in)
24 declare float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float>)
25 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
26 declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>)
31 %max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in)
38 %max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in)
45 %max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in)
49 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)
[all …]
Darm64-vsqrt.ll1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
8 %tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
17 %tmp3 = call <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
26 %tmp3 = call <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
30 declare <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
31 declare <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
32 declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone
40 %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
49 %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
58 %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
[all …]
Delim-dead-mi.mir1 # RUN: llc -mtriple=aarch64-arm-none-eabi -o - %s \
27 %0:gpr64 = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) @c
34 …%1:gpr64common = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) …
48 $x0 = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) @c
58 …; CHECK-NOT: %6:gpr64 = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch…
59 %6:gpr64 = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) @c
Dsve-intrinsics-uqdec.ll1 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s 2>%t | FileCheck %s
8 ; * @llvm.aarch64.sve.uqinc{b|h|w|d|p}, and
9 ; * @llvm.aarch64.sve.uqdec{b|h|w|d|p}
22 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %a,
35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %a,
48 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %a,
61 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdecp.nxv8i16(<vscale x 8 x i16> %a,
70 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecp.nxv4i32(<vscale x 4 x i32> %a,
79 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecp.nxv2i64(<vscale x 2 x i64> %a,
92 %out = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %a, i32 3, i32 4)
[all …]
/external/vixl/test/
Dtest-code-generation-scopes.cc69 aarch64::MacroAssembler masm; in TEST()
72 CodeBufferCheckScope scope(&masm, aarch64::kInstructionSize); in TEST()
73 __ Mov(aarch64::x0, 0); in TEST()
98 aarch64::MacroAssembler masm; in TEST()
101 CodeBufferCheckScope scope(&masm, 2 * aarch64::kInstructionSize); in TEST()
102 __ Mov(aarch64::x0, 0); in TEST()
103 __ movz(aarch64::x1, 1); in TEST()
129 aarch64::MacroAssembler masm; in TEST()
133 __ Mov(aarch64::x0, 0); in TEST()
134 scope.Open(&masm, aarch64::kInstructionSize); in TEST()
[all …]
/external/llvm/test/CodeGen/MIR/AArch64/
Dtarget-flags.mir1 # RUN: llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o …
24 ; CHECK: %x8 = ADRP target-flags(aarch64-page) @var_i32
25 ; CHECK-NEXT: %x9 = ADRP target-flags(aarch64-page) @var_i64
26 ; CHECK-NEXT: %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
27 ; CHECK-NEXT: %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
28 ; CHECK: STRWui killed %w10, killed %x8, target-flags(aarch64-nc) @var_i32
29 ; CHECK: STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
30 %x8 = ADRP target-flags(aarch64-page) @var_i32
31 %x9 = ADRP target-flags(aarch64-page) @var_i64
32 %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
[all …]
/external/llvm-project/llvm/test/CodeGen/MIR/AArch64/
Dtarget-flags.mir1 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
24 ; CHECK: $x8 = ADRP target-flags(aarch64-page) @var_i32
25 ; CHECK-NEXT: $x9 = ADRP target-flags(aarch64-page) @var_i64
26 ; CHECK-NEXT: $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
27 ; CHECK-NEXT: $x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
28 ; CHECK: STRWui killed $w10, killed $x8, target-flags(aarch64-nc) @var_i32
29 ; CHECK: STRXui killed $x11, killed $x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
30 $x8 = ADRP target-flags(aarch64-page) @var_i32
31 $x9 = ADRP target-flags(aarch64-page) @var_i64
32 $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
[all …]
/external/vixl/examples/aarch64/
Dexamples.h37 void GenerateFactorial(vixl::aarch64::MacroAssembler* masm);
43 void GenerateFactorialRec(vixl::aarch64::MacroAssembler* masm);
49 void GenerateNEONMatrixMultiply(vixl::aarch64::MacroAssembler* masm);
55 void GenerateAdd2Vectors(vixl::aarch64::MacroAssembler* masm);
62 void GenerateAdd3Double(vixl::aarch64::MacroAssembler* masm);
69 void GenerateAdd4Double(vixl::aarch64::MacroAssembler* masm);
76 void GenerateSumArray(vixl::aarch64::MacroAssembler* masm);
82 void GenerateAbs(vixl::aarch64::MacroAssembler* masm);
91 void GenerateCheckBounds(vixl::aarch64::MacroAssembler* masm);
98 void GenerateCrc32(vixl::aarch64::MacroAssembler* masm);
[all …]
/external/arm-trusted-firmware/plat/arm/board/arm_fpga/
Dplatform.mk51 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
52 lib/cpus/aarch64/cortex_a53.S \
53 lib/cpus/aarch64/cortex_a57.S \
54 lib/cpus/aarch64/cortex_a72.S \
55 lib/cpus/aarch64/cortex_a73.S
58 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
59 lib/cpus/aarch64/cortex_a76ae.S \
60 lib/cpus/aarch64/cortex_a77.S \
61 lib/cpus/aarch64/cortex_a78.S \
62 lib/cpus/aarch64/neoverse_n_common.S \
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-blockaddress.mir2 # RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select…
3 # RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select…
8 target triple = "aarch64-none-linux-gnu"
33 …= MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-f…
34 …r:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, …
41 …; LARGE: [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@te…
42 …; LARGE: [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) bloc…
43 …; LARGE: [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blo…
44 …; LARGE: [[MOVKXi2:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) blockaddress(@…
45 ; LARGE: [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @addr, 0
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)
18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)
34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)
38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone
39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone
40 declare i32 @llvm.aarch64.neon.fcvtas.i32.f64(double) nounwind readnone
41 declare i64 @llvm.aarch64.neon.fcvtas.i64.f64(double) nounwind readnone
50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
[all …]
Darm64-neon-across.ll3 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
5 declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)
7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
9 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
11 declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)
13 declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)
15 declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)
17 declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)
19 declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>)
[all …]
Darm64-fminv.ll6 %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in)
13 %min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in)
20 %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in)
24 declare float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float>)
25 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
26 declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>)
31 %max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in)
38 %max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in)
45 %max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in)
49 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)
[all …]
Darm64-vsqrt.ll1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
8 %tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
17 %tmp3 = call <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
26 %tmp3 = call <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
30 declare <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
31 declare <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
32 declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone
40 %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
49 %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
58 %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
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/external/vixl/benchmarks/aarch64/
Dbench-utils.h174 explicit BenchCodeGenerator(vixl::aarch64::MacroAssembler* masm) in BenchCodeGenerator()
232 vixl::aarch64::Register PickR(unsigned size_in_bits);
233 vixl::aarch64::VRegister PickV(
234 unsigned size_in_bits = vixl::aarch64::kQRegSize);
236 vixl::aarch64::Register PickW() { return PickR(vixl::aarch64::kWRegSize); } in PickW()
237 vixl::aarch64::Register PickX() { return PickR(vixl::aarch64::kXRegSize); } in PickX()
238 vixl::aarch64::VRegister PickH() { return PickV(vixl::aarch64::kHRegSize); } in PickH()
239 vixl::aarch64::VRegister PickS() { return PickV(vixl::aarch64::kSRegSize); } in PickS()
240 vixl::aarch64::VRegister PickD() { return PickV(vixl::aarch64::kDRegSize); } in PickD()
242 vixl::aarch64::MacroAssembler* masm_;
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/external/XNNPACK/scripts/
Dgenerate-f16-gemm.sh8 tools/xngen src/f16-gemm/1x16-aarch64-neonfp16arith-ld32.S.in -D INC=0 -o src/f16-gemm/gen/1x16-min…
9 tools/xngen src/f16-gemm/4x16-aarch64-neonfp16arith-ld32.S.in -D INC=0 -o src/f16-gemm/gen/4x16-min…
10 tools/xngen src/f16-gemm/6x16-aarch64-neonfp16arith-ld32.S.in -D INC=0 -o src/f16-gemm/gen/6x16-min…
11 tools/xngen src/f16-gemm/1x16-aarch64-neonfp16arith-ld32.S.in -D INC=1 -o src/f16-gemm/gen-inc/1x16…
12 tools/xngen src/f16-gemm/4x16-aarch64-neonfp16arith-ld32.S.in -D INC=1 -o src/f16-gemm/gen-inc/4x16…
13 tools/xngen src/f16-gemm/6x16-aarch64-neonfp16arith-ld32.S.in -D INC=1 -o src/f16-gemm/gen-inc/6x16…
15 tools/xngen src/f16-gemm/1x8-aarch64-neonfp16arith-ld64.S.in -D INC=0 -o src/f16-gemm/gen/1x8-minma…
16 tools/xngen src/f16-gemm/4x8-aarch64-neonfp16arith-ld64.S.in -D INC=0 -o src/f16-gemm/gen/4x8-minma…
17 tools/xngen src/f16-gemm/6x8-aarch64-neonfp16arith-ld64.S.in -D INC=0 -o src/f16-gemm/gen/6x8-minma…
18 tools/xngen src/f16-gemm/8x8-aarch64-neonfp16arith-ld64.S.in -D INC=0 -o src/f16-gemm/gen/8x8-minma…
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