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Searched refs:addImm (Results 1 – 25 of 574) sorted by relevance

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/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
89 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
99 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
101 .addImm(0); in lowerSubvectorStore()
[all …]
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
112 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
122 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
124 .addImm(0); in lowerSubvectorStore()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
112 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
122 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
124 .addImm(0); in lowerSubvectorStore()
[all …]
/external/llvm-project/llvm/lib/Target/VE/
DVEFrameLowering.cpp154 .addImm(0) in emitPrologueInsns()
155 .addImm(0) in emitPrologueInsns()
159 .addImm(0) in emitPrologueInsns()
160 .addImm(8) in emitPrologueInsns()
166 .addImm(0) in emitPrologueInsns()
167 .addImm(24) in emitPrologueInsns()
171 .addImm(0) in emitPrologueInsns()
172 .addImm(32) in emitPrologueInsns()
178 .addImm(0) in emitPrologueInsns()
179 .addImm(40) in emitPrologueInsns()
[all …]
DVEInstrInfo.cpp342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); in copyPhysSubRegs()
362 .addImm(0); in copyPhysReg()
374 .addImm(0) in copyPhysReg()
375 .addImm(0) in copyPhysReg()
376 .addImm(256); in copyPhysReg()
378 .addImm(M1(0)) // Represent (0)1. in copyPhysReg()
459 .addImm(0) in storeRegToStackSlot()
460 .addImm(0) in storeRegToStackSlot()
466 .addImm(0) in storeRegToStackSlot()
467 .addImm(0) in storeRegToStackSlot()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIFrameLowering.cpp156 .addImm(Offset) in buildPrologSpill()
157 .addImm(0) // glc in buildPrologSpill()
158 .addImm(0) // slc in buildPrologSpill()
159 .addImm(0) // dlc in buildPrologSpill()
168 .addImm(Offset) in buildPrologSpill()
169 .addImm(0) // glc in buildPrologSpill()
170 .addImm(0) // slc in buildPrologSpill()
171 .addImm(0) // tfe in buildPrologSpill()
172 .addImm(0) // dlc in buildPrologSpill()
173 .addImm(0) // swz in buildPrologSpill()
[all …]
DAMDGPUInstructionSelector.cpp159 .addImm(1) in selectCOPY()
162 .addImm(0) in selectCOPY()
340 .addImm(0); in selectG_ADD_SUB()
374 .addImm(0); in selectG_ADD_SUB()
380 .addImm(0); in selectG_ADD_SUB()
388 .addImm(AMDGPU::sub0) in selectG_ADD_SUB()
390 .addImm(AMDGPU::sub1); in selectG_ADD_SUB()
526 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
618 .addImm(Lo16 | (Hi16 << 16)); in selectG_BUILD_VECTOR_TRUNC()
665 .addImm(16); in selectG_BUILD_VECTOR_TRUNC()
[all …]
DR600ControlFlowFinalizer.cpp353 .addImm(0) // ADDR in MakeFetchClause()
354 .addImm(AluInstCount - 1); // COUNT in MakeFetchClause()
402 .addImm(LiteralPair0) in insertLiterals()
403 .addImm(LiteralPair1); in insertLiterals()
445 MILit.addImm(Literals[i]->getImm()); in MakeALUClause()
452 MILit.addImm(Literals[i + 1]->getImm()); in MakeALUClause()
458 MILit.addImm(0); in MakeALUClause()
472 BuildMI(BB, DL, TII->get(R600::FETCH_CLAUSE)).addImm(CfCount); in EmitFetchClause()
484 BuildMI(BB, DL, TII->get(R600::ALU_CLAUSE)).addImm(CfCount); in EmitALUClause()
554 .addImm(CfCount + 1) in runOnMachineFunction()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFrameLowering.cpp110 .addImm(Offset) in buildPrologSpill()
111 .addImm(0) // glc in buildPrologSpill()
112 .addImm(0) // slc in buildPrologSpill()
113 .addImm(0) // tfe in buildPrologSpill()
114 .addImm(0) // dlc in buildPrologSpill()
115 .addImm(0) // swz in buildPrologSpill()
124 .addImm(Offset); in buildPrologSpill()
131 .addImm(0) in buildPrologSpill()
132 .addImm(0) // glc in buildPrologSpill()
133 .addImm(0) // slc in buildPrologSpill()
[all …]
DR600ControlFlowFinalizer.cpp354 .addImm(0) // ADDR in MakeFetchClause()
355 .addImm(AluInstCount - 1); // COUNT in MakeFetchClause()
403 .addImm(LiteralPair0) in insertLiterals()
404 .addImm(LiteralPair1); in insertLiterals()
446 MILit.addImm(Literals[i]->getImm()); in MakeALUClause()
453 MILit.addImm(Literals[i + 1]->getImm()); in MakeALUClause()
459 MILit.addImm(0); in MakeALUClause()
473 BuildMI(BB, DL, TII->get(R600::FETCH_CLAUSE)).addImm(CfCount); in EmitFetchClause()
485 BuildMI(BB, DL, TII->get(R600::ALU_CLAUSE)).addImm(CfCount); in EmitALUClause()
555 .addImm(CfCount + 1) in runOnMachineFunction()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp177 .addImm(ARMCC::AL) in runOnMachineFunction()
1006 .addImm(ARMCC::AL) in EmitJumpTableInsts()
1288 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1304 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1315 .addImm(ARMCC::AL) in EmitInstruction()
1352 .addImm(ARMCC::AL).addReg(0) in EmitInstruction()
1361 .addImm(ARMCC::AL) in EmitInstruction()
1370 .addImm(ARMCC::AL) in EmitInstruction()
1381 .addImm(ARMCC::AL) in EmitInstruction()
1394 .addImm(ARMCC::AL) in EmitInstruction()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp187 .addImm(ARMCC::AL) in runOnMachineFunction()
1024 .addImm(ARMCC::AL) in emitJumpTableInsts()
1333 .addImm(MI->getOperand(2).getImm()) in emitInstruction()
1349 .addImm(MI->getOperand(2).getImm()) in emitInstruction()
1360 .addImm(ARMCC::AL) in emitInstruction()
1397 .addImm(ARMCC::AL).addReg(0) in emitInstruction()
1406 .addImm(ARMCC::AL) in emitInstruction()
1415 .addImm(ARMCC::AL) in emitInstruction()
1426 .addImm(ARMCC::AL) in emitInstruction()
1439 .addImm(ARMCC::AL) in emitInstruction()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
DVEFrameLowering.cpp53 .addImm(0) in emitPrologueInsns()
57 .addImm(8) in emitPrologueInsns()
61 .addImm(24) in emitPrologueInsns()
65 .addImm(32) in emitPrologueInsns()
69 .addImm(0); in emitPrologueInsns()
91 .addImm(0); in emitEpilogueInsns()
94 .addImm(32); in emitEpilogueInsns()
97 .addImm(24); in emitEpilogueInsns()
100 .addImm(8); in emitEpilogueInsns()
103 .addImm(0); in emitEpilogueInsns()
[all …]
DVEInstrInfo.cpp95 .addImm(VECC::CC_IGE) in expandExtendStackPseudo()
107 .addImm(0x18); in expandExtendStackPseudo()
110 .addImm(0); in expandExtendStackPseudo()
112 .addImm(0x13b); in expandExtendStackPseudo()
115 .addImm(0) in expandExtendStackPseudo()
119 .addImm(8) in expandExtendStackPseudo()
123 .addImm(16) in expandExtendStackPseudo()
129 .addImm(0); in expandExtendStackPseudo()
/external/llvm/lib/Target/AMDGPU/
DR600ControlFlowFinalizer.cpp339 .addImm(0) // ADDR in MakeFetchClause()
340 .addImm(AluInstCount - 1); // COUNT in MakeFetchClause()
388 .addImm(LiteralPair0) in insertLiterals()
389 .addImm(LiteralPair1); in insertLiterals()
431 MILit.addImm(Literals[i]->getImm()); in MakeALUClause()
438 MILit.addImm(Literals[i + 1]->getImm()); in MakeALUClause()
444 MILit.addImm(0); in MakeALUClause()
459 .addImm(CfCount); in EmitFetchClause()
473 .addImm(CfCount); in EmitALUClause()
541 .addImm(CfCount + 1) in runOnMachineFunction()
[all …]
DR600ISelLowering.cpp307 .addImm(isEOP(I)); // Set End of program bit in EmitInstrWithCustomInserter()
315 .addImm(isEOP(I)); // Set End of program bit in EmitInstrWithCustomInserter()
360 .addImm(SrcX) in EmitInstrWithCustomInserter()
361 .addImm(SrcY) in EmitInstrWithCustomInserter()
362 .addImm(SrcZ) in EmitInstrWithCustomInserter()
363 .addImm(SrcW) in EmitInstrWithCustomInserter()
364 .addImm(0) in EmitInstrWithCustomInserter()
365 .addImm(0) in EmitInstrWithCustomInserter()
366 .addImm(0) in EmitInstrWithCustomInserter()
367 .addImm(0) in EmitInstrWithCustomInserter()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrBuilder.h127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
187 MIB.addImm(AM.Disp); in addFullAddress()
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrBuilder.h127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
187 MIB.addImm(AM.Disp); in addFullAddress()
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h122 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
128 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
162 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
166 MIB.addImm(AM.Disp); in addFullAddress()
205 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp80 .addImm(I * Alignment); in expandMEMCPY()
83 .addImm(I * Alignment); in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
137 .addImm(0); in storeRegToStackSlot()
142 .addImm(0); in storeRegToStackSlot()
[all …]
/external/llvm-project/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp80 .addImm(I * Alignment); in expandMEMCPY()
83 .addImm(I * Alignment); in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
137 .addImm(0); in storeRegToStackSlot()
142 .addImm(0); in storeRegToStackSlot()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp301 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8)); in EmitSled()
304 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in EmitSled()
374 .addImm(4) in EmitHwasanMemaccessSymbols()
375 .addImm(55), in EmitHwasanMemaccessSymbols()
381 .addImm(0) in EmitHwasanMemaccessSymbols()
382 .addImm(0), in EmitHwasanMemaccessSymbols()
389 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)), in EmitHwasanMemaccessSymbols()
394 .addImm(AArch64CC::NE) in EmitHwasanMemaccessSymbols()
408 .addImm(15) in EmitHwasanMemaccessSymbols()
409 .addImm(0), in EmitHwasanMemaccessSymbols()
[all …]
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp164 .addImm(ARMCC::AL) in runOnMachineFunction()
1074 .addImm(ARMCC::AL) in EmitJumpTableInsts()
1314 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1330 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1341 .addImm(ARMCC::AL) in EmitInstruction()
1377 .addImm(ARMCC::AL).addReg(0) in EmitInstruction()
1386 .addImm(ARMCC::AL) in EmitInstruction()
1395 .addImm(ARMCC::AL) in EmitInstruction()
1406 .addImm(ARMCC::AL) in EmitInstruction()
1419 .addImm(ARMCC::AL) in EmitInstruction()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp282 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8)); in EmitSled()
285 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in EmitSled()
365 .addImm(4) in EmitHwasanMemaccessSymbols()
366 .addImm(55), in EmitHwasanMemaccessSymbols()
373 .addImm(0) in EmitHwasanMemaccessSymbols()
374 .addImm(0), in EmitHwasanMemaccessSymbols()
381 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)), in EmitHwasanMemaccessSymbols()
386 .addImm(AArch64CC::NE) in EmitHwasanMemaccessSymbols()
400 .addImm(56) in EmitHwasanMemaccessSymbols()
401 .addImm(63), in EmitHwasanMemaccessSymbols()
[all …]
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiFrameLowering.cpp80 .addImm(MaxCallFrameSize); in replaceAdjDynAllocPseudo()
116 .addImm(-4) in emitPrologue()
117 .addImm(LPAC::makePreOp(LPAC::ADD)) in emitPrologue()
124 .addImm(8) in emitPrologue()
132 .addImm(StackSize) in emitPrologue()
188 .addImm(0); in emitEpilogue()
193 .addImm(-8) in emitEpilogue()
194 .addImm(LPAC::ADD); in emitEpilogue()

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