| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 279 .addUse(TiedDest) in buildUnalignedLoad()
334 .addUse(PseudoMULTuReg); in select()
363 .addUse(Mips::ZERO) in select()
376 .addUse(I.getOperand(2).getReg()) in select()
384 .addUse(I.getOperand(0).getReg()) in select()
385 .addUse(JTIndex); in select()
393 .addUse(DestAddress) in select()
405 .addUse(DestTmp) in select()
406 .addUse(MF.getInfo<MipsFunctionInfo>() in select()
414 .addUse(Dest); in select()
[all …]
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| D | MipsISelLowering.cpp | 4754 .addUse(Address) in emitLDR_W()
4756 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); in emitLDR_W()
4766 .addUse(Address) in emitLDR_W()
4768 .addUse(Undef); in emitLDR_W()
4771 .addUse(Address) in emitLDR_W()
4773 .addUse(LoadHalf); in emitLDR_W()
4774 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); in emitLDR_W()
4801 .addUse(Address) in emitLDR_D()
4803 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); in emitLDR_D()
4810 .addUse(Address) in emitLDR_D()
[all …]
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| D | MipsSEISelDAGToDAG.cpp | 135 .addUse(Mips::RA_64, RegState::Undef) in emitMCountABI()
136 .addUse(Mips::ZERO_64); in emitMCountABI()
138 MIB.addUse(Mips::AT_64, RegState::Implicit); in emitMCountABI()
143 .addUse(Mips::RA, RegState::Undef) in emitMCountABI()
144 .addUse(Mips::ZERO); in emitMCountABI()
148 .addUse(Mips::SP) in emitMCountABI()
151 MIB.addUse(Mips::AT, RegState::Implicit); in emitMCountABI()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SpeculationHardening.cpp | 233 .addUse(MisspeculatingTaintReg) in insertTrackingCode()
234 .addUse(AArch64::XZR) in insertTrackingCode()
371 .addUse(AArch64::SP) in insertSPToRegTaintPropagation()
377 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
378 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
394 .addUse(AArch64::SP) in insertRegToSPTaintPropagation()
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable) in insertRegToSPTaintPropagation()
401 .addUse(MisspeculatingTaintReg, RegState::Kill) in insertRegToSPTaintPropagation()
406 .addUse(TmpReg, RegState::Kill) in insertRegToSPTaintPropagation()
454 .addUse(Reg); in makeGPRSpeculationSafe()
[all …]
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| D | AArch64ExpandPseudoInsts.cpp | 300 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
301 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
308 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
309 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
312 .addUse(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP_128()
582 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB); in expandSetTagLoop()
811 .addUse(DstReg, RegState::Kill); in expandMI()
981 .addUse(SrcReg) in expandMI()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SpeculationHardening.cpp | 233 .addUse(MisspeculatingTaintReg) in insertTrackingCode()
234 .addUse(AArch64::XZR) in insertTrackingCode()
371 .addUse(AArch64::SP) in insertSPToRegTaintPropagation()
377 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
378 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
394 .addUse(AArch64::SP) in insertRegToSPTaintPropagation()
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable) in insertRegToSPTaintPropagation()
401 .addUse(MisspeculatingTaintReg, RegState::Kill) in insertRegToSPTaintPropagation()
406 .addUse(TmpReg, RegState::Kill) in insertRegToSPTaintPropagation()
454 .addUse(Reg); in makeGPRSpeculationSafe()
[all …]
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| D | AArch64InstructionSelector.cpp | 756 .addUse(SrcReg) in selectCopy()
1029 .addUse(LHS) in selectCompareBranch()
1129 Shl.addUse(Src2Reg); in selectVectorSHL()
1201 .addUse(ArgsAddrReg) in selectVaStartDarwin()
1202 .addUse(ListReg) in selectVaStartDarwin()
1230 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
1513 .addUse(CondReg) in select()
1522 .addUse(CondReg) in select()
1761 .addUse(I.getOperand(2).getReg()) in select()
1908 .addUse(LdReg) in select()
[all …]
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| D | AArch64ExpandPseudoInsts.cpp | 295 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
296 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
303 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
304 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
307 .addUse(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP_128()
379 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB); in expandSetTagLoop()
520 .addUse(DstReg, RegState::Kill); in expandMI()
693 .addUse(SrcReg) in expandMI()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 299 .addUse(PseudoMULTuReg); in select()
328 .addUse(Mips::ZERO) in select()
341 .addUse(I.getOperand(2).getReg()) in select()
349 .addUse(I.getOperand(0).getReg()) in select()
350 .addUse(JTIndex); in select()
358 .addUse(DestAddress) in select()
370 .addUse(DestTmp) in select()
371 .addUse(MF.getInfo<MipsFunctionInfo>() in select()
379 .addUse(Dest); in select()
459 .addUse(HILOReg); in select()
[all …]
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| D | MipsCallLowering.cpp | 150 .addUse(PhysReg + (STI.isLittle() ? 0 : 1)) in assignValueToReg()
151 .addUse(PhysReg + (STI.isLittle() ? 1 : 0)) in assignValueToReg()
159 .addUse(PhysReg) in assignValueToReg()
262 .addUse(ValVReg) in assignValueToReg()
270 .addUse(ValVReg) in assignValueToReg()
277 .addUse(ValVReg) in assignValueToReg()
283 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
579 MIB.addUse(CalleeReg); in lowerCall()
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| D | MipsSEISelDAGToDAG.cpp | 135 .addUse(Mips::RA_64, RegState::Undef) in emitMCountABI()
136 .addUse(Mips::ZERO_64); in emitMCountABI()
138 MIB.addUse(Mips::AT_64, RegState::Implicit); in emitMCountABI()
143 .addUse(Mips::RA, RegState::Undef) in emitMCountABI()
144 .addUse(Mips::ZERO); in emitMCountABI()
148 .addUse(Mips::SP) in emitMCountABI()
151 MIB.addUse(Mips::AT, RegState::Implicit); in emitMCountABI()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1215 .addUse(GetReg) in getSegmentAperture()
1216 .addUse(ShiftAmt.getReg(0)); in getSegmentAperture()
1345 .addUse(Src); in legalizeAddrSpaceCast()
1422 .addUse(Const0.getReg(0)) in extractF64Exponent()
1423 .addUse(Const1.getReg(0)); in extractF64Exponent()
1497 .addUse(CvtHi.getReg(0)) in legalizeITOFP()
1498 .addUse(ThirtyTwo.getReg(0)); in legalizeITOFP()
1604 .addUse(MulVal.getReg(0)) in legalizeSinCos()
1612 .addUse(TrigVal) in legalizeSinCos()
1798 .addUse(PtrReg) in legalizeAtomicCmpXChg()
[all …]
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| D | AMDGPURegisterBankInfo.cpp | 694 .addUse(Reg); in split64BitValueForMapping()
1413 .addUse(VData); in selectStoreIntrinsic()
1416 MIB.addUse(VOffset); in selectStoreIntrinsic()
1418 MIB.addUse(RSrc) in selectStoreIntrinsic()
1419 .addUse(SOffset) in selectStoreIntrinsic()
1443 .addUse(SrcReg); in buildVCopy()
1453 .addUse(SrcReg, 0, AMDGPU::sub0); in buildVCopy()
1456 .addUse(SrcReg, 0, AMDGPU::sub1); in buildVCopy()
1459 .addUse(TmpReg0) in buildVCopy()
1461 .addUse(TmpReg1) in buildVCopy()
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1943 .addUse(Hi) in extractF64Exponent()
1944 .addUse(Const0.getReg(0)) in extractF64Exponent()
1945 .addUse(Const1.getReg(0)); in extractF64Exponent()
2017 .addUse(CvtHi.getReg(0)) in legalizeITOFP()
2018 .addUse(ThirtyTwo.getReg(0)); in legalizeITOFP()
2177 .addUse(MulVal.getReg(0)) in legalizeSinCos()
2185 .addUse(TrigVal) in legalizeSinCos()
2483 .addUse(PtrReg) in legalizeAtomicCmpXChg()
2484 .addUse(PackedVal) in legalizeAtomicCmpXChg()
2533 .addUse(Log.getReg(0)) in legalizeFPow()
[all …]
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| /external/llvm/lib/IR/ |
| D | Use.cpp | 28 Val->addUse(*this); in swap()
35 RHS.Val->addUse(RHS); in swap()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | Use.cpp | 27 Val->addUse(*this); in swap()
34 RHS.Val->addUse(RHS); in swap()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 259 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
268 .addUse(TablePtr) in buildBrJT()
270 .addUse(IndexReg); in buildBrJT()
357 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); in buildBrCond()
658 .addUse(Src) in buildInsert()
659 .addUse(Op) in buildInsert()
756 .addUse(Addr) in buildAtomicCmpXchgWithSuccess()
757 .addUse(CmpVal) in buildAtomicCmpXchgWithSuccess()
758 .addUse(NewVal) in buildAtomicCmpXchgWithSuccess()
781 .addUse(Addr) in buildAtomicCmpXchg()
[all …]
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 581 .addUse(LHSReg) in insertComparison()
582 .addUse(RHSReg) in insertComparison()
600 .addUse(PrevRes) in insertComparison()
778 .addUse(CondReg) in selectSelect()
794 .addUse(TrueReg) in selectSelect()
795 .addUse(FalseReg) in selectSelect()
888 .addUse(AndResult) in select()
938 .addUse(SrcReg) in select()
1109 .addUse(OriginalValue) in select()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 583 .addUse(LHSReg) in insertComparison()
584 .addUse(RHSReg) in insertComparison()
602 .addUse(PrevRes) in insertComparison()
780 .addUse(CondReg) in selectSelect()
796 .addUse(TrueReg) in selectSelect()
797 .addUse(FalseReg) in selectSelect()
890 .addUse(AndResult) in select()
940 .addUse(SrcReg) in select()
1111 .addUse(OriginalValue) in select()
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| /external/llvm-project/llvm/unittests/CodeGen/GlobalISel/ |
| D | CSETest.cpp | 95 .addUse(Copies[0]) in TEST_F()
96 .addUse(Copies[1]); in TEST_F()
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| D | MachineIRBuilderTest.cpp | 169 .addUse(Copies[0]); in TEST_F()
175 .addUse(Copies[1]); in TEST_F()
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 909 .addUse(SrcReg) in selectCopy()
1739 Shl.addUse(Src2Reg); in selectVectorSHL()
1827 .addUse(ArgsAddrReg) in selectVaStartDarwin()
1828 .addUse(ListReg) in selectVaStartDarwin()
1856 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
2476 .addUse(I.getOperand(2).getReg()) in select()
2589 IsStore ? NewInst.addUse(ValReg) : NewInst.addDef(ValReg); in select()
2634 .addUse(LdReg) in select()
2866 .addUse(SrcReg) in select()
2927 .addUse(SrcReg) in select()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 224 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
233 .addUse(TablePtr) in buildBrJT()
235 .addUse(IndexReg); in buildBrJT()
785 .addUse(Addr) in buildAtomicCmpXchgWithSuccess()
786 .addUse(CmpVal) in buildAtomicCmpXchgWithSuccess()
787 .addUse(NewVal) in buildAtomicCmpXchgWithSuccess()
810 .addUse(Addr) in buildAtomicCmpXchg()
811 .addUse(CmpVal) in buildAtomicCmpXchg()
812 .addUse(NewVal) in buildAtomicCmpXchg()
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| /external/skia/src/gpu/ |
| D | GrResourceAllocator.h | 211 void addUse() { fUses++; } in addUse() function
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| D | GrResourceAllocator.cpp | 89 intvl->addUse();
97 newIntvl->addUse();
|