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Searched refs:amt2 (Results 1 – 25 of 63) sorted by relevance

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/external/libyuv/files/util/
Dcompare.cc39 int amt2 = 0; in main() local
46 amt2 = static_cast<int>(fread(buf2, 1, kBlockSize, fin2)); in main()
47 if (amt2 > 0) { in main()
48 hash2 = libyuv::HashDjb2(buf2, amt2, hash2); in main()
50 int amt_min = (amt1 < amt2) ? amt1 : amt2; in main()
54 } while (amt1 > 0 || amt2 > 0); in main()
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrCall.td20 defm ADJCALLSTACKDOWN : NRI<(outs), (ins i32imm:$amt, i32imm:$amt2),
21 [(WebAssemblycallseq_start timm:$amt, timm:$amt2)]>;
22 defm ADJCALLSTACKUP : NRI<(outs), (ins i32imm:$amt, i32imm:$amt2),
23 [(WebAssemblycallseq_end timm:$amt, timm:$amt2)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrCall.td20 defm ADJCALLSTACKDOWN : NRI<(outs), (ins i32imm:$amt, i32imm:$amt2),
21 [(WebAssemblycallseq_start timm:$amt, timm:$amt2)]>;
22 defm ADJCALLSTACKUP : NRI<(outs), (ins i32imm:$amt, i32imm:$amt2),
23 [(WebAssemblycallseq_end timm:$amt, timm:$amt2)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
DVEInstrInfo.td273 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt, i64imm:$amt2),
274 "# ADJCALLSTACKDOWN $amt, $amt2",
275 [(callseq_start timm:$amt, timm:$amt2)]>;
276 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
278 [(callseq_end timm:$amt1, timm:$amt2)]>;
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrCall.td24 def ADJCALLSTACKUP : I<(outs), (ins i32imm:$amt, i32imm:$amt2),
25 [(WebAssemblycallseq_end timm:$amt, timm:$amt2)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td549 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
550 "#ADJCALLSTACKDOWN $amt1 $amt2",
551 [(BPFcallseq_start timm:$amt1, timm:$amt2)]>;
552 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
553 "#ADJCALLSTACKUP $amt1 $amt2",
554 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td753 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
754 "#ADJCALLSTACKDOWN $amt1 $amt2",
755 [(CallSeqStart timm:$amt1, timm:$amt2)]>;
756 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
757 "#ADJCALLSTACKUP $amt1 $amt2",
758 [(CallSeqEnd timm:$amt1, timm:$amt2)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td753 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
754 "#ADJCALLSTACKDOWN $amt1 $amt2",
755 [(CallSeqStart timm:$amt1, timm:$amt2)]>;
756 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
757 "#ADJCALLSTACKUP $amt1 $amt2",
758 [(CallSeqEnd timm:$amt1, timm:$amt2)]>;
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1090 // 32-bit software rotate by immediate. $amt2 should equal 32 - $amt1.
1093 (ins Int32Regs:$src, i32imm:$amt1, i32imm:$amt2),
1098 "shr.b32 \t%rhs, $src, $amt2;\n\t"
1120 ".reg .b32 %amt2;\n\t"
1122 "sub.s32 \t%amt2, 32, $amt;\n\t"
1123 "shr.b32 \t%rhs, $src, %amt2;\n\t"
1135 ".reg .b32 %amt2;\n\t"
1137 "sub.s32 \t%amt2, 32, $amt;\n\t"
1138 "shl.b32 \t%rhs, $src, %amt2;\n\t"
1144 // 64-bit software rotate by immediate. $amt2 should equal 64 - $amt1.
[all …]
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1219 // 32-bit software rotate by immediate. $amt2 should equal 32 - $amt1.
1222 (ins Int32Regs:$src, i32imm:$amt1, i32imm:$amt2),
1227 "shr.b32 \t%rhs, $src, $amt2;\n\t"
1249 ".reg .b32 %amt2;\n\t"
1251 "sub.s32 \t%amt2, 32, $amt;\n\t"
1252 "shr.b32 \t%rhs, $src, %amt2;\n\t"
1264 ".reg .b32 %amt2;\n\t"
1266 "sub.s32 \t%amt2, 32, $amt;\n\t"
1267 "shl.b32 \t%rhs, $src, %amt2;\n\t"
1273 // 64-bit software rotate by immediate. $amt2 should equal 64 - $amt1.
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1219 // 32-bit software rotate by immediate. $amt2 should equal 32 - $amt1.
1222 (ins Int32Regs:$src, i32imm:$amt1, i32imm:$amt2),
1227 "shr.b32 \t%rhs, $src, $amt2;\n\t"
1249 ".reg .b32 %amt2;\n\t"
1251 "sub.s32 \t%amt2, 32, $amt;\n\t"
1252 "shr.b32 \t%rhs, $src, %amt2;\n\t"
1264 ".reg .b32 %amt2;\n\t"
1266 "sub.s32 \t%amt2, 32, $amt;\n\t"
1267 "shl.b32 \t%rhs, $src, %amt2;\n\t"
1273 // 64-bit software rotate by immediate. $amt2 should equal 64 - $amt1.
[all …]
/external/llvm-project/llvm/lib/Target/BPF/
DBPFInstrInfo.td549 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
550 "#ADJCALLSTACKDOWN $amt1 $amt2",
551 [(BPFcallseq_start timm:$amt1, timm:$amt2)]>;
552 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
553 "#ADJCALLSTACKUP $amt1 $amt2",
554 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td443 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
444 "#ADJCALLSTACKUP $amt1 $amt2",
445 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
/external/llvm-project/llvm/lib/Target/ARC/
DARCInstrInfo.td88 def ADJCALLSTACKDOWN : PseudoInstARC<(outs), (ins i32imm:$amt, i32imm:$amt2),
89 "# ADJCALLSTACKDOWN $amt, $amt2",
90 [(callseq_start timm:$amt, timm:$amt2)]>;
91 def ADJCALLSTACKUP : PseudoInstARC<(outs), (ins i32imm:$amt1, i32imm:$amt2),
93 [(callseq_end timm:$amt1, timm:$amt2)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCInstrInfo.td88 def ADJCALLSTACKDOWN : PseudoInstARC<(outs), (ins i32imm:$amt, i32imm:$amt2),
89 "# ADJCALLSTACKDOWN $amt, $amt2",
90 [(callseq_start timm:$amt, timm:$amt2)]>;
91 def ADJCALLSTACKUP : PseudoInstARC<(outs), (ins i32imm:$amt1, i32imm:$amt2),
93 [(callseq_end timm:$amt1, timm:$amt2)]>;
/external/llvm-project/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td174 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
175 "#ADJCALLSTACKDOWN $amt1 $amt2",
176 [(MSP430callseq_start timm:$amt1, timm:$amt2)]>;
177 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
178 "#ADJCALLSTACKUP $amt1 $amt2",
179 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td174 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
175 "#ADJCALLSTACKDOWN $amt1 $amt2",
176 [(MSP430callseq_start timm:$amt1, timm:$amt2)]>;
177 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
178 "#ADJCALLSTACKUP $amt1 $amt2",
179 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
/external/llvm-project/llvm/lib/Target/XCore/
DXCoreInstrInfo.td326 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt, i32imm:$amt2),
327 "# ADJCALLSTACKDOWN $amt, $amt2",
328 [(callseq_start timm:$amt, timm:$amt2)]>;
329 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
331 [(callseq_end timm:$amt1, timm:$amt2)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrInfo.td326 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt, i32imm:$amt2),
327 "# ADJCALLSTACKDOWN $amt, $amt2",
328 [(callseq_start timm:$amt, timm:$amt2)]>;
329 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
331 [(callseq_end timm:$amt1, timm:$amt2)]>;
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPseudo.td82 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
86 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td82 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
86 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrCompiler.td41 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
43 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
45 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
48 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;
59 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
61 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
63 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
66 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrCompiler.td41 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
43 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
45 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
48 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;
59 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
61 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
63 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
66 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td759 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
760 "#ADJCALLSTACKUP $amt1 $amt2",
761 [(CallSeqEnd timm:$amt1, timm:$amt2)]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td1053 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1054 [(callseq_start timm:$amt1, timm:$amt2)]>;
1055 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1056 [(callseq_end timm:$amt1, timm:$amt2)]>;

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