| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | and.ll | 42 ; MM: and16 $[[T0:[0-9]+]], $5
57 ; MM: and16 $[[T0:[0-9]+]], $5
72 ; MM: and16 $[[T0:[0-9]+]], $5
88 ; MM32: and16 $[[T0:[0-9]+]], $5
107 ; MM32: and16 $[[T0:[0-9]+]], $6
108 ; MM32: and16 $[[T1:[0-9]+]], $7
136 ; MM32: and16 $[[T1]], $4
137 ; MM32: and16 $[[T0]], $5
139 ; MM32: and16 $[[T2]], $6
141 ; MM32: and16 $[[T3]], $7
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | optimize-andiso.ll | 29 %and16 = and i64 %inc, 67108864
30 %tobool = icmp eq i64 %and16, 0
|
| /external/llvm-project/llvm/test/MC/Mips/ |
| D | micromips-16-bit-instructions.s | 15 # CHECK-EL: and16 $16, $2 # encoding: [0x82,0x44]
70 # CHECK-EB: and16 $16, $2 # encoding: [0x44,0x82]
123 and16 $16, $2
|
| D | micromips-invalid.s | 12 and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/ |
| D | micromips-16-bit-instructions.s | 15 # CHECK-EL: and16 $16, $2 # encoding: [0x82,0x44]
70 # CHECK-EB: and16 $16, $2 # encoding: [0x44,0x82]
123 and16 $16, $2
|
| D | micromips-invalid.s | 12 and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | micromips-and16.ll | 18 ; CHECK: and16
|
| /external/llvm/test/CodeGen/Mips/ |
| D | micromips-and16.ll | 18 ; CHECK: and16
|
| /external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | and.ll | 69 ; MM32R3-NEXT: and16 $4, $5
118 ; MM32R3-NEXT: and16 $4, $5
167 ; MM32R3-NEXT: and16 $4, $5
213 ; MM32R3-NEXT: and16 $4, $5
262 ; MM32R3-NEXT: and16 $4, $6
263 ; MM32R3-NEXT: and16 $5, $7
336 ; MM32R3-NEXT: and16 $2, $4
337 ; MM32R3-NEXT: and16 $3, $5
339 ; MM32R3-NEXT: and16 $4, $6
341 ; MM32R3-NEXT: and16 $5, $7
[all …]
|
| /external/llvm/test/Transforms/SimplifyCFG/ |
| D | merge-cond-stores-2.ll | 83 %and16 = and i32 %4, 16
84 %tobool17 = icmp eq i32 %and16, 0
|
| /external/llvm-project/llvm/test/Transforms/SimplifyCFG/ |
| D | merge-cond-stores-2.ll | 191 %and16 = and i32 %4, 16
192 %tobool17 = icmp eq i32 %and16, 0
|
| /external/llvm-project/llvm/test/MC/Mips/micromips/ |
| D | valid.s | 22 and16 $16, $2 # CHECK: and16 $16, $2 # encoding: [0x44,0x82] label
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | valid.s | 13 and16 $16, $2 # CHECK: and16 $16, $2 # encoding: [0x44,0x21]
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid-el.txt | 13 0x82 0x44 # CHECK: and16 $16, $2
|
| D | valid.txt | 13 0x44 0x82 # CHECK: and16 $16, $2
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | valid.s | 247 and16 $16, $2 # CHECK: and16 $16, $2 # encoding: [0x44,0x21]
|
| /external/llvm-project/llvm/test/MC/Mips/micromips32r6/ |
| D | valid.s | 296 and16 $16, $2 # CHECK: and16 $16, $2 # encoding: [0x44,0x21]
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid-el.txt | 13 0x82 0x44 # CHECK: and16 $16, $2
|
| D | valid.txt | 13 0x44 0x82 # CHECK: and16 $16, $2
|
| /external/llvm/test/MC/Disassembler/Mips/micromips64r6/ |
| D | valid.txt | 12 0x44 0x21 # CHECK: and16 $16, $2
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 26 0x44 0x21 # CHECK: and16 $16, $2
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 26 0x44 0x21 # CHECK: and16 $16, $2
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 1089 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
1090 MMR6Arch<"and16"> {
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 1093 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
1094 MMR6Arch<"and16">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 1093 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
1094 MMR6Arch<"and16">;
|