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/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_shift.txt10 # CHECK: r17:16 = asl(r21:20, #31)
16 # CHECK: r17 = asl(r21, #31)
24 # CHECK: r17:16 -= asl(r21:20, #31)
30 # CHECK: r17:16 += asl(r21:20, #31)
36 # CHECK: r17 -= asl(r21, #31)
42 # CHECK: r17 += asl(r21, #31)
44 # CHECK: r17 = add(#21, asl(r17, #23))
46 # CHECK: r17 = sub(#21, asl(r17, #23))
62 # CHECK: r17:16 &= asl(r21:20, #31)
68 # CHECK: r17:16 |= asl(r21:20, #31)
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/Hexagon/
Dxtype_shift.txt10 # CHECK: r17:16 = asl(r21:20,#31)
16 # CHECK: r17 = asl(r21,#31)
24 # CHECK: r17:16 -= asl(r21:20,#31)
30 # CHECK: r17:16 += asl(r21:20,#31)
36 # CHECK: r17 -= asl(r21,#31)
42 # CHECK: r17 += asl(r21,#31)
44 # CHECK: r17 = add(#21,asl(r17,#23))
46 # CHECK: r17 = sub(#21,asl(r17,#23))
62 # CHECK: r17:16 &= asl(r21:20,#31)
68 # CHECK: r17:16 |= asl(r21:20,#31)
[all …]
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_shift.ll22 declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32)
24 %z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0)
27 ; CHECK: = asl({{.*}}, #0)
43 declare i32 @llvm.hexagon.S2.asl.i.r(i32, i32)
45 %z = call i32 @llvm.hexagon.S2.asl.i.r(i32 %a, i32 0)
48 ; CHECK: = asl({{.*}}, #0)
65 declare i64 @llvm.hexagon.S2.asl.i.p.nac(i64, i64, i32)
67 %z = call i64 @llvm.hexagon.S2.asl.i.p.nac(i64 %a, i64 %b, i32 0)
70 ; CHECK: -= asl({{.*}}, #0)
86 declare i64 @llvm.hexagon.S2.asl.i.p.acc(i64, i64, i32)
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_shift.ll22 declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32)
24 %z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0)
27 ; CHECK: = asl({{.*}},#0)
43 declare i32 @llvm.hexagon.S2.asl.i.r(i32, i32)
45 %z = call i32 @llvm.hexagon.S2.asl.i.r(i32 %a, i32 0)
48 ; CHECK: = asl({{.*}},#0)
65 declare i64 @llvm.hexagon.S2.asl.i.p.nac(i64, i64, i32)
67 %z = call i64 @llvm.hexagon.S2.asl.i.p.nac(i64 %a, i64 %b, i32 0)
70 ; CHECK: -= asl({{.*}},#0)
86 declare i64 @llvm.hexagon.S2.asl.i.p.acc(i64, i64, i32)
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dextract-element.ll7 ; CHECK-DAG: r[[R002:[0-9]+]] = asl(r[[R000]],#3)
19 ; CHECK-DAG: r[[R102:[0-9]+]] = asl(r[[R100]],#3)
29 ; CHECK-DAG: r[[R010:[0-9]+]] = asl(r0,#1)
32 ; CHECK: r[[R013:[0-9]+]] = asl(r[[R011]],#4)
42 ; CHECK-DAG: r[[R110:[0-9]+]] = asl(r0,#1)
45 ; CHECK: r[[R113:[0-9]+]] = asl(r[[R111]],#4)
55 ; CHECK: [[R020:r[0-9]+]] = asl(r0,#2)
64 ; CHECK: [[R120:r[0-9]+]] = asl(r0,#2)
/external/llvm-project/compiler-rt/lib/builtins/hexagon/
Ddfsqrt.S130 FRACRAD = asl(FRACRAD,SHIFTAMT) // Move fracrad bits to right place
136 PROD = asl(FRACRAD,SHIFTAMT) // fracrad<<(2+exp1)
146 RECIPEST = asl(SF_H,SHIFTAMT)
175 ERROR = asl(FRACRAD,#15)
180 ERROR -= asl(PROD,#15)
194 ERROR = asl(FRACRAD,#31) // for next iter
202 ERROR -= asl(PROD,#31)
214 ERROR = asl(FRACRAD,#47) // for next iter
221 ERROR -= asl(PROD,#47)
225 ERROR -= asl(PROD,#16) // bidir shr 31-47
[all …]
Ddffma.S280 PP_LL = asl(PP_LL,#62)
292 CTMP = asl(PP_HH,LEFTSHIFT)
293 STICKIES |= asl(PP_LL,LEFTSHIFT)
317 AH += asl(EXPA,#HI_MANTBITS)
358 AH += asl(EXPA,#HI_MANTBITS)
405 ATMP = asl(ATMP,EXPB) // shift left
438 AH += asl(TMP,#HI_MANTBITS)
556 BTMP = asl(BTMP,TMP)
560 AH -= asl(TMP,#HI_MANTBITS)
578 A ^= asl(B,#63)
[all …]
Ddfdiv.S154 REM = asl(REM,# ## ( REMSHIFT )); \
163 REM -= asl(REMSUB2, # ## 32); \
218 AH += asl(EXPA,#DF_MANTBITS-32)
224 AH += asl(EXPA,#DF_MANTBITS-32)
256 PROD = asl(PROD,EXPB)
283 AH += asl(TMP,#DF_MANTBITS-32)
420 A = asl(A,QH)
421 B = asl(B,QL)
Ddfmul.S74 BTMP = asl(B,#EXPBITS-1)
133 AH += asl(EXP0,#HI_MANTBITS)
177 AH += asl(EXP1,#HI_MANTBITS)
338 BTMP = asl(BTMP,TMP)
342 AH -= asl(TMP,#HI_MANTBITS)
403 AH ^= asl(BH,#31)
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Drotate-multi.ll21 ; CHECK: r1 |= asl(r0,#7)
38 ; CHECK: r[[R20:[0-9]+]] = asl(r0,#11)
41 ; CHECK: r[[R20]] |= asl(r1,#19)
57 ; CHECK: r[[R30:[0-9]+]] = asl(r0,#3)
58 ; CHECK: r[[R30]] |= asl(r0,#5)
59 ; CHECK: r[[R30]] |= asl(r0,#7)
60 ; CHECK: r[[R30]] |= asl(r0,#13)
61 ; CHECK: r[[R30]] |= asl(r0,#19)
Dfunnel-shift.ll5 ; CHECK: r[[R02:[0-9]+]]:[[R03:[0-9]+]] = asl(r[[R00]]:[[R01]],#17)
14 ; CHECK: r[[R12:[0-9]+]]:[[R13:[0-9]+]] = asl(r[[R10]]:[[R11]],r2)
22 ; CHECK: r[[R20:[0-9]+]]:[[R21:[0-9]+]] = asl(r1:0,#17)
31 ; CHECK: r[[R30:[0-9]+]]:[[R31:[0-9]+]] = asl(r1:0,r4)
60 ; CHECK: r[[R60]]:[[R61]] |= asl(r1:0,#47)
70 ; CHECK: r[[R70]]:[[R71]] |= asl(r1:0,r6)
87 ; CHECK: r[[R92:[0-9]+]]:[[R93:[0-9]+]] = asl(r[[R90]]:[[R91]],r1)
103 ; CHECK: r[[RB0:[0-9]+]]:[[RB1:[0-9]+]] = asl(r1:0,r2)
140 ; CHECK: r[[RF0]]:[[RF1]] |= asl(r1:0,r[[RF2]])
Dsubi-asl.ll7 ; XCHECK: [[REG1:(r[0-9]+)]] = sub(#0,asl([[REG1]],#1))
8 ; CHECK: [[REG1:(r[0-9]+)]] = asl([[REG1]],#1)
12 ; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}},#1)
Drdf-def-mask.ll21 %v7 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 %v6)
23 %v9 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 %v5)
48 declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1
Dhwloop-crit-edge.ll14 %2 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %1, i32 -13)
32 %8 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %7, i32 -13)
54 declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1
Drotate.ll18 ; CHECK: r[[R12:[0-9]+]]:[[R13:[0-9]+]] = asl(r[[R10]]:[[R11]],r1)
64 ; CHECK: r[[R50:[0-9]+]]:[[R51:[0-9]+]] = asl(r1:0,r2)
92 ; CHECK: r[[R70]]:[[R71]] |= asl(r1:0,r[[R72]])
139 ; CHECK: r0 |= asl(r1,#7)
195 ; CHECK: r1:0 |= asl(r3:2,#7)
/external/llvm-project/llvm/test/CodeGen/Hexagon/vect/
Dvect-shift-imm.ll21 %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
24 %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6)
35 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone
38 declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone
Dvect-vshifts.ll24 %9 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %8, i32 1)
48 %20 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %19, i32 %gb)
77 %31 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %30, i32 %gb)
106 %42 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %41, i32 %gb)
135 %53 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %52, i32 %gb)
164 %64 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %63, i32 %gb)
193 %75 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %74, i32 %gb)
222 %86 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %85, i32 %gb)
251 %97 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %96, i32 %gb)
264 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1
[all …]
Dvect-load-v4i16.ll7 ; CHECK: r2 |= asl([[T1]],#16)
10 ; CHECK: r1 |= asl([[T3]],#16)
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-shift-imm.ll21 %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
24 %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6)
35 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone
38 declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone
Dvect-vshifts.ll24 %9 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %8, i32 1)
48 %20 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %19, i32 %gb)
77 %31 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %30, i32 %gb)
106 %42 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %41, i32 %gb)
135 %53 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %52, i32 %gb)
164 %64 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %63, i32 %gb)
193 %75 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %74, i32 %gb)
222 %86 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %85, i32 %gb)
251 %97 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %96, i32 %gb)
264 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1
[all …]
/external/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dlattice_armv7.S45 add r0, r9, asl #1 @ Restore r0 to &ar_g_Q0[order_coef]
46 add r2, r9, asl #1 @ Restore r2 to &cth_Q15[order_coef]
47 add r3, r9, asl #1 @ Restore r3 to &sth_Q15[order_coef]
/external/webrtc/common_audio/signal_processing/
Dcomplex_bit_reverse_arm.S33 mov r1, r3, asl r1 @ n = 1 << stages;
55 mov r12, r4, asl #2
71 add r4, r3, r4, asl #1
/external/llvm-project/llvm/test/MC/Disassembler/ARC/
Dalu.txt36 # CHECK: asl %r1, %r1, 2
39 # CHECK: asl %r0, %r0, %r0
42 # CHECK: asl.f %r0, %r0, %r0
/external/strace/
Dmpers_test.sh61 long asl[3][5][7];
108 int${size}_t asl[3][5][7];
/external/llvm/test/CodeGen/Hexagon/
Dhwloop-crit-edge.ll13 %2 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %1, i32 -13)
31 %8 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %7, i32 -13)
53 declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1

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