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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dasr.s10 asr z0.b, z0.b, #1 label
16 asr z31.b, z31.b, #8 label
22 asr z0.h, z0.h, #1 label
28 asr z31.h, z31.h, #16 label
34 asr z0.s, z0.s, #1 label
40 asr z31.s, z31.s, #32 label
46 asr z0.d, z0.d, #1 label
52 asr z31.d, z31.d, #64 label
58 asr z0.b, p0/m, z0.b, #1 label
64 asr z31.b, p0/m, z31.b, #8 label
[all …]
Dasr-diagnostics.s3 asr z30.b, z10.b, #0 label
8 asr z18.b, z27.b, #9 label
13 asr z18.b, p0/m, z28.b, #0 label
18 asr z1.b, p0/m, z9.b, #9 label
23 asr z26.h, z4.h, #0 label
28 asr z25.h, z10.h, #17 label
33 asr z21.h, p0/m, z2.h, #0 label
38 asr z14.h, p0/m, z30.h, #17 label
43 asr z17.s, z0.s, #0 label
48 asr z0.s, z15.s, #33 label
[all …]
/external/llvm-project/llvm/test/MC/AVR/
Dinst-asr.s7 asr r31
8 asr r25
9 asr r5
10 asr r0
12 ; CHECK: asr r31 ; encoding: [0xf5,0x95]
13 ; CHECK: asr r25 ; encoding: [0x95,0x95]
14 ; CHECK: asr r5 ; encoding: [0x55,0x94]
15 ; CHECK: asr r0 ; encoding: [0x05,0x94]
17 ; CHECK-INST: asr r31
18 ; CHECK-INST: asr r25
[all …]
/external/mesa3d/src/intel/tools/tests/gen6/
Dasr.asm1 asr(8) g11<1>D g11<4>D 16D { align16 1Q };
2 asr(8) g2<1>D g2<8,8,1>D 16D { align1 1Q };
3 asr(16) g2<1>D g2<8,8,1>D 16D { align1 1H };
4 asr(8) g6<1>D g5<8,8,1>D 0x00000001UD { align1 1Q };
5 asr(16) g8<1>D g6<8,8,1>D 0x00000001UD { align1 1H };
6 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
7 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
8 asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q };
9 asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H };
10 asr(8) g26<1>D g25<4>D g20<4>UD { align16 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dasr.asm1 asr(8) g13<1>.xD g5.4<0>.zD g5.4<0>.wUD { align16 1Q };
2 asr(8) g57<1>.xD g38<4>.xD 0x00000001UD { align16 1Q };
3 asr(8) g3<1>D g2<0,1,0>D g2.1<0,1,0>UD { align1 1Q };
4 asr(16) g3<1>D g2<0,1,0>D g2.1<0,1,0>UD { align1 1H };
5 asr(8) g6<1>D g5<8,8,1>D 0x00000001UD { align1 1Q };
6 asr(16) g8<1>D g6<8,8,1>D 0x00000001UD { align1 1H };
7 asr(8) g4<1>.xD g14<4>.xD 0x00000010UD { align16 NoDDClr 1Q };
8 asr(8) g4<1>.yD g1<0>.xD 0x00000010UD { align16 NoDDChk 1Q };
9 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
10 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
[all …]
/external/mesa3d/src/intel/tools/tests/gen7/
Dasr.asm1 asr(8) g13<1>.xD g5.4<0>.zD g5.4<0>.wUD { align16 1Q };
2 asr(8) g57<1>.xD g38<4>.xD 0x00000001UD { align16 1Q };
3 asr(8) g6<1>D g5<8,8,1>D 0x00000001UD { align1 1Q };
4 asr(16) g8<1>D g6<8,8,1>D 0x00000001UD { align1 1H };
5 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
6 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
7 asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q };
8 asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H };
/external/llvm-project/llvm/test/CodeGen/X86/
Datomic-dagsched.ll15 %asr.iv6 = phi i8* [ %29, %test.exit ], [ %scevgep, %entry ]
35 %asr.iv9 = phi i8* [ %scevgep10, %vector_kernel_entry.i ], [ %asr.iv6, %dim_0_vector_pre_head.i ]
36 …%asr.iv = phi i64 [ %asr.iv.next, %vector_kernel_entry.i ], [ %vector.size.i, %dim_0_vector_pre_he…
38 %asr.iv911 = addrspacecast i8* %asr.iv9 to <8 x i32> addrspace(1)*
39 %9 = load <8 x i32>, <8 x i32> addrspace(1)* %asr.iv911, align 4
56 store <8 x i32> %vectorvector_func.i, <8 x i32> addrspace(1)* %asr.iv911, align 4
57 %asr.iv.next = add i64 %asr.iv, -1
58 %scevgep10 = getelementptr i8, i8* %asr.iv9, i64 32
59 %dim_0_vector_cmp.to.max.i = icmp eq i64 %asr.iv.next, 0
75 %asr.iv12 = phi i64 [ %asr.iv.next13, %scalar_kernel_entry.i ], [ %22, %dim_0_pre_head.i ]
[all …]
/external/llvm/test/CodeGen/X86/
Datomic-dagsched.ll15 %asr.iv6 = phi i8* [ %29, %test.exit ], [ %scevgep, %entry ]
35 %asr.iv9 = phi i8* [ %scevgep10, %vector_kernel_entry.i ], [ %asr.iv6, %dim_0_vector_pre_head.i ]
36 …%asr.iv = phi i64 [ %asr.iv.next, %vector_kernel_entry.i ], [ %vector.size.i, %dim_0_vector_pre_he…
38 %asr.iv911 = addrspacecast i8* %asr.iv9 to <8 x i32> addrspace(1)*
39 %9 = load <8 x i32>, <8 x i32> addrspace(1)* %asr.iv911, align 4
56 store <8 x i32> %vectorvector_func.i, <8 x i32> addrspace(1)* %asr.iv911, align 4
57 %asr.iv.next = add i64 %asr.iv, -1
58 %scevgep10 = getelementptr i8, i8* %asr.iv9, i64 32
59 %dim_0_vector_cmp.to.max.i = icmp eq i64 %asr.iv.next, 0
75 %asr.iv12 = phi i64 [ %asr.iv.next13, %scalar_kernel_entry.i ], [ %22, %dim_0_pre_head.i ]
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Darm-shift-encoding.s8 ldr r0, [r0, r0, asr #32]
9 ldr r0, [r0, r0, asr #16]
18 @ CHECK: ldr r0, [r0, r0, asr #32] @ encoding: [0x40,0x00,0x90,0xe7]
19 @ CHECK: ldr r0, [r0, r0, asr #16] @ encoding: [0x40,0x08,0x90,0xe7]
28 pld [r0, r0, asr #32]
29 pld [r0, r0, asr #16]
38 @ CHECK: [r0, r0, asr #32] @ encoding: [0x40,0xf0,0xd0,0xf7]
39 @ CHECK: [r0, r0, asr #16] @ encoding: [0x40,0xf8,0xd0,0xf7]
48 str r0, [r0, r0, asr #32]
49 str r0, [r0, r0, asr #16]
[all …]
/external/llvm/test/MC/ARM/
Darm-shift-encoding.s8 ldr r0, [r0, r0, asr #32]
9 ldr r0, [r0, r0, asr #16]
18 @ CHECK: ldr r0, [r0, r0, asr #32] @ encoding: [0x40,0x00,0x90,0xe7]
19 @ CHECK: ldr r0, [r0, r0, asr #16] @ encoding: [0x40,0x08,0x90,0xe7]
28 pld [r0, r0, asr #32]
29 pld [r0, r0, asr #16]
38 @ CHECK: [r0, r0, asr #32] @ encoding: [0x40,0xf0,0xd0,0xf7]
39 @ CHECK: [r0, r0, asr #16] @ encoding: [0x40,0xf8,0xd0,0xf7]
48 str r0, [r0, r0, asr #32]
49 str r0, [r0, r0, asr #16]
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-logical-encoding.s56 and w1, w2, w3, asr #2
57 and x1, x2, x3, asr #2
67 ; CHECK: and w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x0a]
68 ; CHECK: and x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0x8a]
78 ands w1, w2, w3, asr #2
79 ands x1, x2, x3, asr #2
89 ; CHECK: ands w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x6a]
90 ; CHECK: ands x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0xea]
100 bic w1, w2, w3, asr #3
101 bic x1, x2, x3, asr #3
[all …]
/external/llvm/test/MC/AArch64/
Darm64-logical-encoding.s56 and w1, w2, w3, asr #2
57 and x1, x2, x3, asr #2
67 ; CHECK: and w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x0a]
68 ; CHECK: and x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0x8a]
78 ands w1, w2, w3, asr #2
79 ands x1, x2, x3, asr #2
89 ; CHECK: ands w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x6a]
90 ; CHECK: ands x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0xea]
100 bic w1, w2, w3, asr #3
101 bic x1, x2, x3, asr #3
[all …]
/external/libxaac/decoder/armv7/
Dixheaacd_decorr_filter2.s165 MOV r7, r9, asr #15
166 MOV r8, r3, asr #15
172 MOV r14, r14, asr #16
173 MOV r1, r1, asr #16
190 MOV r3, r3, asr #15
195 MOV r9, r9, asr #15
197 SUB r3, r3, r14, asr #15
198 SUB r9, r9, r1, asr #15
205 ADD r14, r7, r14, asr #15
208 ADD r1, r8, r1, asr #15
[all …]
/external/capstone/suite/MC/ARM/
Darm-shift-encoding.s.cs7 0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #32]
8 0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #16]
16 0x40,0xf0,0xd0,0xf7 = pld [r0, r0, asr #32]
17 0x40,0xf8,0xd0,0xf7 = pld [r0, r0, asr #16]
25 0x40,0x00,0x80,0xe7 = str r0, [r0, r0, asr #32]
26 0x40,0x08,0x80,0xe7 = str r0, [r0, r0, asr #16]
38 0x4b,0x50,0xa4,0xe0 = adc r5, r4, r11, asr #32
39 0x4d,0x68,0xa3,0xe0 = adc r6, r3, sp, asr #16
47 0x44,0x00,0x55,0xe1 = cmp r5, r4, asr #32
48 0x43,0x08,0x56,0xe1 = cmp r6, r3, asr #16
/external/llvm-project/compiler-rt/lib/builtins/arm/
Ddivmodsi4.S52 eor ip, r0, r0, asr #31
53 eor lr, r1, r1, asr #31
54 sub r0, ip, r0, asr #31
55 sub r1, lr, r1, asr #31
60 eor r0, r0, r4, asr #31
61 eor r1, r1, r5, asr #31
62 sub r0, r0, r4, asr #31
63 sub r1, r1, r5, asr #31
Dmodsi3.S45 eor r2, r0, r0, asr #31
46 eor r3, r1, r1, asr #31
47 sub r0, r2, r0, asr #31
48 sub r1, r3, r1, asr #31
52 eor r0, r0, r4, asr #31
53 sub r0, r0, r4, asr #31
/external/compiler-rt/lib/builtins/arm/
Ddivmodsi4.S59 eor ip, r0, r0, asr #31
60 eor lr, r1, r1, asr #31
61 sub r0, ip, r0, asr #31
62 sub r1, lr, r1, asr #31
67 eor r0, r0, r4, asr #31
68 eor r1, r1, r5, asr #31
69 sub r0, r0, r4, asr #31
70 sub r1, r1, r5, asr #31
/external/mesa3d/src/intel/tools/tests/gen5/
Dasr.asm1 asr.nz.f0.0(8) null<1>D -g1.6<0,1,0>D 31D { align1 };
2 asr.nz.f0.0(16) null<1>D -g1.6<0,1,0>D 31D { align1 compr };
3 asr(8) g4<1>D g5<4>D g4<4>UD { align16 };
4 asr(8) g11<1>.xD g5<4>.xD 0x00000002UD { align16 };
5 asr(8) g5<1>D g3<8,8,1>D 0x00000002UD { align1 };
6 asr(16) g10<1>D g6<8,8,1>D 0x00000002UD { align1 compr };
/external/mesa3d/src/intel/tools/tests/gen9/
Dasr.asm1 asr(8) g19<1>D g7<8,8,1>D 0x00000001UD { align1 1Q };
2 asr(16) g20<1>D g2.7<0,1,0>D 0x0000001fUD { align1 1H };
3 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
4 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
5 asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q };
6 asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H };
/external/mesa3d/src/intel/tools/tests/gen8/
Dasr.asm1 asr(8) g19<1>D g7<8,8,1>D 0x00000001UD { align1 1Q };
2 asr(16) g20<1>D g2.7<0,1,0>D 0x0000001fUD { align1 1H };
3 asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q };
4 asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H };
5 asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q };
6 asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H };
/external/llvm-project/llvm/test/CodeGen/AVR/
Dsmul-with-overflow.ll16 ; CHECK: asr {{.*}}[[LOW]]
17 ; CHECK: asr {{.*}}[[LOW]]
18 ; CHECK: asr {{.*}}[[LOW]]
19 ; CHECK: asr {{.*}}[[LOW]]
20 ; CHECK: asr {{.*}}[[LOW]]
21 ; CHECK: asr {{.*}}[[LOW]]
22 ; CHECK: asr {{.*}}[[LOW]]
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_shift.ll8 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32)
10 %z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0)
13 ; CHECK: = asr({{.*}}, #0)
29 declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32)
31 %z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0)
34 ; CHECK: = asr({{.*}}, #0)
51 declare i64 @llvm.hexagon.S2.asr.i.p.nac(i64, i64, i32)
53 %z = call i64 @llvm.hexagon.S2.asr.i.p.nac(i64 %a, i64 %b, i32 0)
56 ; CHECK: -= asr({{.*}}, #0)
72 declare i64 @llvm.hexagon.S2.asr.i.p.acc(i64, i64, i32)
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_shift.ll8 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32)
10 %z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0)
13 ; CHECK: = asr({{.*}},#0)
29 declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32)
31 %z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0)
34 ; CHECK: = asr({{.*}},#0)
51 declare i64 @llvm.hexagon.S2.asr.i.p.nac(i64, i64, i32)
53 %z = call i64 @llvm.hexagon.S2.asr.i.p.nac(i64 %a, i64 %b, i32 0)
56 ; CHECK: -= asr({{.*}},#0)
72 declare i64 @llvm.hexagon.S2.asr.i.p.acc(i64, i64, i32)
[all …]
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_shift.txt6 # CHECK: r17:16 = asr(r21:20, #31)
12 # CHECK: r17 = asr(r21, #31)
20 # CHECK: r17:16 -= asr(r21:20, #31)
26 # CHECK: r17:16 += asr(r21:20, #31)
32 # CHECK: r17 -= asr(r21, #31)
38 # CHECK: r17 += asr(r21, #31)
58 # CHECK: r17:16 &= asr(r21:20, #31)
64 # CHECK: r17:16 |= asr(r21:20, #31)
74 # CHECK: r17 &= asr(r21, #31)
80 # CHECK: r17 |= asr(r21, #31)
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/Hexagon/
Dxtype_shift.txt6 # CHECK: r17:16 = asr(r21:20,#31)
12 # CHECK: r17 = asr(r21,#31)
20 # CHECK: r17:16 -= asr(r21:20,#31)
26 # CHECK: r17:16 += asr(r21:20,#31)
32 # CHECK: r17 -= asr(r21,#31)
38 # CHECK: r17 += asr(r21,#31)
58 # CHECK: r17:16 &= asr(r21:20,#31)
64 # CHECK: r17:16 |= asr(r21:20,#31)
74 # CHECK: r17 &= asr(r21,#31)
80 # CHECK: r17 |= asr(r21,#31)
[all …]

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