| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb-instructions.s.cs | 20 0x1a,0x10 = asrs r2, r3, #32
21 0x5a,0x11 = asrs r2, r3, #5
22 0x5a,0x10 = asrs r2, r3, #1
23 0x6d,0x15 = asrs r5, r5, #21
24 0x6d,0x15 = asrs r5, r5, #21
25 0x6b,0x15 = asrs r3, r5, #21
26 0x15,0x41 = asrs r5, r2
|
| D | thumb2-narrow-dp.ll.cs | 152 0x56,0xfa,0x05,0xf7 = asrs.w r7, r6, r5
153 0x08,0x41 = asrs r0, r1
154 0x51,0xfa,0x00,0xf0 = asrs.w r0, r1, r0
155 0x53,0xfa,0x01,0xf3 = asrs.w r3, r3, r1
156 0x51,0xfa,0x01,0xf1 = asrs.w r1, r1, r1
159 0x51,0xfa,0x08,0xf8 = asrs.w r8, r1, r8
160 0x58,0xfa,0x01,0xf8 = asrs.w r8, r8, r1
161 0x58,0xfa,0x05,0xf5 = asrs.w r5, r8, r5
162 0x55,0xfa,0x08,0xf5 = asrs.w r5, r5, r8
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | sdiv-pow2-thumb-size.ll | 72 ; T2-NEXT: asrs r0, r0, #1
80 ; T1-NEXT: asrs r0, r0, #1
90 ; T2: asrs r1, r0, #31
92 ; T2-NEXT: asrs r0, r0, #2
96 ; T1: asrs r1, r0, #31
99 ; T1-NEXT: asrs r0, r0, #2
|
| D | v6m-smul-with-overflow.ll | 11 ; CHECK: asrs r1, r0, #31
12 ; CHECK: asrs r3, r2, #31
|
| D | sat-to-bitop.ll | 20 ; CHECK-T-NEXT: asrs r1, r0, #31
48 ; CHECK-T-NEXT: asrs r1, r1, #16
82 ; CHECK-T-NEXT: asrs r1, r1, #24
113 ; CHECK-T-NEXT: asrs r1, r0, #31
143 ; CHECK-T-NEXT: asrs r1, r0, #31
173 ; CHECK-T-NEXT: asrs r2, r2, #16
211 ; CHECK-T-NEXT: asrs r2, r2, #24
244 ; CHECK-T-NEXT: asrs r1, r0, #31
|
| /external/llvm-project/llvm/test/CodeGen/Thumb/ |
| D | iabs.ll | 8 ; CHECK-NEXT: asrs r1, r1, #7
22 ; CHECK-NEXT: asrs r1, r1, #15
35 ; CHECK-NEXT: asrs r1, r0, #31
48 ; CHECK-NEXT: asrs r2, r1, #31
|
| D | ldr_ext.ll | 27 ; V5: asrs
39 ; V5: asrs
|
| D | 2012-04-26-M0ISelBug.ll | 7 ; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 104 asrs r2, r3, #32
105 asrs r2, r3, #5
106 asrs r2, r3, #1
107 asrs r5, #21
108 asrs r5, r5, #21
109 asrs r3, r5, #21
111 @ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
112 @ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
113 @ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10]
114 @ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
[all …]
|
| D | thumb_rewrites.s | 77 asrs r0, r0, r1
78 @ CHECK: asrs r0, r1 @ encoding: [0x08,0x41]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 104 asrs r2, r3, #32
105 asrs r2, r3, #5
106 asrs r2, r3, #1
107 asrs r5, #21
108 asrs r5, r5, #21
109 asrs r3, r5, #21
111 @ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
112 @ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
113 @ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10]
114 @ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
[all …]
|
| D | thumb_rewrites.s | 77 asrs r0, r0, r1
78 @ CHECK: asrs r0, r1 @ encoding: [0x08,0x41]
|
| /external/llvm-project/compiler-rt/lib/builtins/arm/ |
| D | divsi3.S | 53 asrs r2, r0, #31
54 asrs r3, r1, #31
69 asrs r4, #31
|
| /external/llvm-project/llvm/test/CodeGen/Thumb2/ |
| D | mve-vecreduce-add.ll | 60 ; CHECK-NEXT: asrs r1, r0, #31
188 ; CHECK-NEXT: asrs r0, r0, #31
193 ; CHECK-NEXT: asrs r1, r0, #31
203 ; CHECK-NEXT: asrs r1, r1, #31
208 ; CHECK-NEXT: asrs r3, r1, #31
220 ; CHECK-NEXT: asrs r2, r2, #31
225 ; CHECK-NEXT: asrs r3, r2, #31
272 ; CHECK-NEXT: asrs r1, r0, #31
505 ; CHECK-NEXT: asrs r0, r0, #31
510 ; CHECK-NEXT: asrs r1, r0, #31
[all …]
|
| D | mve-sext-masked-load.ll | 62 ; CHECK-NEXT: asrs r1, r0, #31
66 ; CHECK-NEXT: asrs r3, r2, #31
74 ; CHECK-NEXT: asrs r3, r2, #31
80 ; CHECK-NEXT: asrs r3, r2, #31
|
| D | mve-vecreduce-addpred.ll | 85 ; CHECK-NEXT: asrs r0, r0, #31
89 ; CHECK-NEXT: asrs r0, r0, #31
349 ; CHECK-NEXT: asrs r1, r1, #31
354 ; CHECK-NEXT: asrs r1, r1, #31
374 ; CHECK-NEXT: asrs r0, r0, #31
379 ; CHECK-NEXT: asrs r0, r0, #31
411 ; CHECK-NEXT: asrs r3, r3, #31
416 ; CHECK-NEXT: asrs r3, r3, #31
438 ; CHECK-NEXT: asrs r2, r2, #31
443 ; CHECK-NEXT: asrs r2, r2, #31
[all …]
|
| D | thumb2-asr2.ll | 5 ; CHECK: asrs r0, r0, #17
|
| D | thumb2-asr.ll | 5 ; CHECK: asrs r0, r1
|
| /external/llvm/test/CodeGen/Thumb/ |
| D | ldr_ext.ll | 27 ; V5: asrs
39 ; V5: asrs
|
| D | 2012-04-26-M0ISelBug.ll | 7 ; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 67 # CHECK: asrs r2, r3, #32
68 # CHECK: asrs r2, r3, #5
69 # CHECK: asrs r2, r3, #1
78 # CHECK: asrs r5, r2
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 67 # CHECK: asrs r2, r3, #32
68 # CHECK: asrs r2, r3, #5
69 # CHECK: asrs r2, r3, #1
78 # CHECK: asrs r5, r2
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-asr2.ll | 5 ; CHECK: asrs r0, r0, #17
|
| D | thumb2-asr.ll | 5 ; CHECK: asrs r0, r1
|
| D | thumb2-lsr3.ll | 14 ; CHECK: asrs.w r1, r1, #1
|