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/external/llvm-project/llvm/test/MC/AMDGPU/
Dvintrp.s4 v_interp_p1_f32 v1, v0, attr0.x
8 v_interp_p1_f32 v2, v0, attr0.y
12 v_interp_p1_f32 v3, v0, attr0.z
16 v_interp_p1_f32 v4, v0, attr0.w
20 v_interp_p1_f32 v5, v0, attr0.x
45 v_interp_p2_f32 v2, v1, attr0.x
49 v_interp_p2_f32 v3, v1, attr0.y
53 v_interp_p2_f32 v4, v1, attr0.z
57 v_interp_p2_f32 v5, v1, attr0.w
61 v_interp_p2_f32 v6, v1, attr0.x
[all …]
Dvop3.s679 v_interp_mov_f32_e64 v5, p10, attr0.x
687 v_interp_mov_f32_e64 v5, p20, attr0.x
691 v_interp_mov_f32_e64 v5, p10, attr0.w
695 v_interp_mov_f32_e64 v5, p10, attr0.x clamp
699 v_interp_mov_f32 v5, p10, attr0.x clamp
703 v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
707 v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
711 v_interp_mov_f32_e64 v5, p10, attr0.x div:2
715 v_interp_mov_f32 v5, p10, attr0.x div:2
720 v_interp_p1_f32_e64 v5, v2, attr0.x
[all …]
Dvintrp-err.s16 v_interp_p2_f32 v0, v1, attr0.q
19 v_interp_p2_f32 v0, v1, attr0.
32 v_interp_mov_f32 v11, invalid_param_3, attr0.y
35 v_interp_mov_f32 v12, invalid_param_10, attr0.x
38 v_interp_mov_f32 v3, invalid_param_3, attr0.x
41 v_interp_mov_f32 v8, invalid_param_8, attr0.x
44 v_interp_mov_f32 v8, foo, attr0.x
Dvop3-errs.s60 v_interp_mov_f32_e64 v5, p10, attr0.x high
64 v_interp_mov_f32_e64 v5, p10, attr0.x v0
68 v_interp_p1_f32_e64 v5, v2, attr0.x high
72 v_interp_p1_f32_e64 v5, v2, attr0.x v0
76 v_interp_p2_f32_e64 v255, v2, attr0.x high
80 v_interp_p2_f32_e64 v255, v2, attr0.x v0
Dvop3-gfx9.s539 v_interp_p2_f16 v5, v2, attr0.x, v3
544 v_interp_p2_f16 v5, -v2, attr0.x, v3
549 v_interp_p2_f16 v5, v2, attr0.x, |v3|
554 v_interp_p2_f16 v5, v2, attr0.w, v3
559 v_interp_p2_f16 v5, v2, attr0.x, v3 high
564 v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
573 v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3
577 v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3|
581 v_interp_p2_legacy_f16 v5, v2, attr0.w, v3
585 v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high
[all …]
Dgfx10_err_pos.s446 v_interp_mov_f32 v11, invalid_param_3, attr0.y
451 v_interp_mov_f32 v8, foo, attr0.x
Dgfx7_unsupported.s1792 v_interp_p1ll_f16 v255, v2, attr0.x
1795 v_interp_p1lv_f16 v255, v2, attr0.x, v3
1798 v_interp_p2_f16 v255, v2, attr0.x, v3
1801 v_interp_p2_legacy_f16 v255, v2, attr0.x, v3
2549 v_interp_mov_f32_e64 v255, p10, attr0.x
2552 v_interp_p1_f32_e64 v255, v2, attr0.x
2555 v_interp_p2_f32_e64 v255, v2, attr0.x
/external/tensorflow/tensorflow/lite/delegates/gpu/common/transformations/
Dmake_fully_connected_test.cc40 Convolution2DAttributes attr0; in TEST() local
41 attr0.padding.prepended = HW(0, 0); in TEST()
42 attr0.padding.appended = HW(0, 0); in TEST()
43 attr0.strides = HW(1, 1); in TEST()
44 attr0.dilations = HW(1, 1); in TEST()
45 attr0.weights.shape = OHWI(16, 1, 1, 8); in TEST()
46 attr0.bias.shape = Linear(16); in TEST()
66 conv1x1_node0->operation.attributes = attr0; in TEST()
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dvintrp.txt24 # VI: v_interp_p1_f32_e32 v0, v0, attr0.x
27 # VI: v_interp_p1_f32_e32 v0, v0, attr0.x
30 # VI: v_interp_p1_f32_e32 v0, v1, attr0.x
33 # VI: v_interp_p1_f32_e32 v0, v1, attr0.w
36 # VI: v_interp_p2_f32_e32 v0, v1, attr0.x
39 # VI: v_interp_mov_f32_e32 v0, p20, attr0.x
Dvop3_vi.txt318 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
324 # VI: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
327 # VI: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
330 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x0…
333 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x0…
336 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x0…
339 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x0…
342 # VI: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
348 # VI: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
351 # VI: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
[all …]
Dvop3_gfx9.txt636 # GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
639 # GFX9: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44]
642 # GFX9: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04]
645 # GFX9: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04]
648 # GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x…
651 # GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0…
657 # GFX9: v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e…
660 # GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0…
663 # GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,…
666 # GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,…
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.interp.ll9 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
10 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
11 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
12 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p0, attr0.x{{$}}
29 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
30 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
31 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.z{{$}}
32 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.w{{$}}
33 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
74 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
[all …]
Ddivergent-branch-uniform-condition.ll24 ; ISA-NEXT: v_interp_p1_f32_e32 v0, v1, attr0.x
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dfunc-attr.mlir4 // CHECK-SAME: tf._implements = #tf.func<@symbol_a, {attr0 = 1 : i32, attr1 = "random"}>
5 func @func_attr() attributes {tf._implements = #tf.func<@symbol_a, {attr0 = 1 : i32, attr1 = "rando…
10 // CHECK-SAME: tf._implements = #tf.func<@symbol_a, {attr0 = 1 : i32, attr1 = "random", nested = #t…
11 func @nested_func_attr() attributes {tf._implements = #tf.func<@symbol_a, {attr0 = 1 : i32, attr1 =…
/external/llvm-project/llvm/test/Reduce/
Dremove-function-attributes.ll7 ; CHECK-INTERESTINGNESS-SAME: "attr0"
14 ; CHECK-FINAL: declare "attr0" void @f0(i32, i32 "attr6") #0
16 declare "attr0" "attr1" "attr2" void @f0(i32 "attr3" "attr4" "attr5", i32 "attr6" "attr7" "attr8") …
Dremove-global-variable-attributes.ll14 ; CHECK-INTERESTINGNESS-SAME: "attr0"
20 ; CHECK-FINAL: attributes #0 = { "attr0" "attr2" }
25 attributes #0 = { "attr0" "attr1" "attr2"}
Dremove-call-site-attributes.ll11 ; CHECK-FINAL-NEXT: %r = call "attr0" i32 @f1(i32 "attr4" %arg0, i32 %arg1) #0
19 ; CHECK-INTERESTINGNESS-SAME: "attr0"
29 …%r = call "attr0" "attr1" "attr2" i32 @f1(i32 "attr3" "attr4" "attr5" %arg0, i32 "attr6" "attr7" "…
/external/tensorflow/tensorflow/lite/delegates/gpu/common/tasks/special/
Dfc_fc_add.cc174 const FullyConnectedAttributes& attr0, in CreateFCFCAdd() argument
177 result.UploadWeights(attr0.weights, "weights0", in CreateFCFCAdd()
185 desc0.UploadLinearData(attr0.bias); in CreateFCFCAdd()
Dfc_fc_add.h113 const FullyConnectedAttributes& attr0,
175 const FullyConnectedAttributes& attr0,
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.interp.p1.f16.ll63 ; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x
70 ; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x
76 ; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr0.x
78 ; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr0.x, v1
/external/llvm-project/llvm/docs/AMDGPU/
Dgfx7_attr.rst28 v_interp_p1_f32 v1, v0, attr0.x
Dgfx8_attr.rst28 v_interp_p1_f32 v1, v0, attr0.x
Dgfx10_attr.rst28 v_interp_p1_f32 v1, v0, attr0.x
Dgfx9_attr.rst28 v_interp_p1_f32 v1, v0, attr0.x
/external/libiio/src/
Dlocal.c182 const char *attr0; in set_channel_name() local
190 attr0 = ptr = chn->attrs[0].name; in set_channel_name()
192 attr0 = ptr = pdata->protected_attrs[0].name; in set_channel_name()
202 len = ptr - attr0 + 1; in set_channel_name()
204 can_fix = !strncmp(attr0, chn->attrs[i].name, len); in set_channel_name()
208 can_fix = !strncmp(attr0, in set_channel_name()
225 strncpy(name, attr0, prefix_len - 1); in set_channel_name()

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