Searched refs:attr_chan (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 351 // __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0>
359 // __builtin_amdgcn_interp_p2 <p1>, <j>, <attr_chan>, <attr>, <m0>
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 1220 // __builtin_amdgcn_interp_mov <param>, <attr_chan>, <attr>, <m0>
1228 // __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0>
1237 // __builtin_amdgcn_interp_p2 <p1>, <j>, <attr_chan>, <attr>, <m0>
1245 // __builtin_amdgcn_interp_p1_f16 <i>, <attr_chan>, <attr>, <high>, <m0>
1252 // __builtin_amdgcn_interp_p2_f16 <p1>, <j>, <attr_chan>, <attr>, <high>, <m0>
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| /external/llvm-project/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 1304 // __builtin_amdgcn_interp_mov <param>, <attr_chan>, <attr>, <m0>
1313 // __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0>
1323 // __builtin_amdgcn_interp_p2 <p1>, <j>, <attr_chan>, <attr>, <m0>
1332 // __builtin_amdgcn_interp_p1_f16 <i>, <attr_chan>, <attr>, <high>, <m0>
1340 // __builtin_amdgcn_interp_p2_f16 <p1>, <j>, <attr_chan>, <attr>, <high>, <m0>
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| /external/mesa3d/src/gallium/drivers/swr/ |
| D | swr_shader.cpp | 1143 Value* attr_chan = GEP(pCpOut, {C(0), C(ScalarPatch_cp), vert_chan_index, in swr_tcs_llvm_fetch_output() local
1146 res = VINSERT(res, LOAD(attr_chan), C(lane)); in swr_tcs_llvm_fetch_output()
1286 Value* attr_chan = GEP(pCpOut, {C(0), C(ScalarPatch_cp), in swr_tcs_llvm_store_output() local
1293 Value *originalVal = LOAD(attr_chan); in swr_tcs_llvm_store_output()
1297 STORE(value_to_store, attr_chan); in swr_tcs_llvm_store_output()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 1437 (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr),
1438 "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]",
1439 [(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan),
1460 (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
1461 "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
1462 [(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan),
1470 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr),
1471 "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]",
1472 [(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan),
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