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Searched refs:aux_usage (Results 1 – 25 of 41) sorted by relevance

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/external/mesa3d/src/intel/isl/
Disl_surface_state.c317 s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || in isl_genX()
318 info->aux_usage == ISL_AUX_USAGE_STC_CCS; in isl_genX()
561 assert(info->aux_usage == ISL_AUX_USAGE_NONE); in isl_genX()
589 if (info->aux_usage != ISL_AUX_USAGE_NONE) { in isl_genX()
592 assert(info->aux_usage == ISL_AUX_USAGE_MCS || in isl_genX()
593 info->aux_usage == ISL_AUX_USAGE_CCS_E || in isl_genX()
594 info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || in isl_genX()
595 info->aux_usage == ISL_AUX_USAGE_MC || in isl_genX()
596 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || in isl_genX()
597 info->aux_usage == ISL_AUX_USAGE_MCS_CCS || in isl_genX()
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Disl_drm.c95 .aux_usage = ISL_AUX_USAGE_CCS_E,
102 .aux_usage = ISL_AUX_USAGE_GEN12_CCS_E,
109 .aux_usage = ISL_AUX_USAGE_MC,
Disl.h1198 enum isl_aux_usage aux_usage; member
1396 enum isl_aux_usage aux_usage; member
1854 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE; in isl_drm_modifier_has_aux()
1885 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE) in isl_drm_modifier_get_default_aux_state()
1888 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E || in isl_drm_modifier_get_default_aux_state()
1889 mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || in isl_drm_modifier_get_default_aux_state()
1890 mod_info->aux_usage == ISL_AUX_USAGE_MC); in isl_drm_modifier_get_default_aux_state()
/external/mesa3d/src/gallium/drivers/iris/
Diris_resolve.c141 enum isl_aux_usage aux_usage = in resolve_image_views() local
147 aux_usage, false); in resolve_image_views()
241 enum isl_aux_usage aux_usage = in iris_predraw_resolve_framebuffer() local
245 if (ice->state.draw_aux_usage[i] != aux_usage) { in iris_predraw_resolve_framebuffer()
246 ice->state.draw_aux_usage[i] = aux_usage; in iris_predraw_resolve_framebuffer()
255 aux_usage); in iris_predraw_resolve_framebuffer()
258 aux_usage); in iris_predraw_resolve_framebuffer()
320 enum isl_aux_usage aux_usage = ice->state.draw_aux_usage[i]; in iris_postdraw_update_resolve_tracking() local
328 aux_usage); in iris_postdraw_update_resolve_tracking()
334 format_aux_tuple(enum isl_format format, enum isl_aux_usage aux_usage) in format_aux_tuple() argument
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Diris_resource.h379 enum isl_aux_usage aux_usage,
407 enum isl_aux_usage aux_usage);
477 res->mod_info->aux_usage != ISL_AUX_USAGE_NONE; in iris_resource_unfinished_aux_import()
511 enum isl_aux_usage aux_usage);
515 enum isl_aux_usage aux_usage);
Diris_blit.c235 enum isl_aux_usage aux_usage, in iris_blorp_surf_for_resource() argument
243 if (isl_aux_usage_has_hiz(aux_usage) && in iris_blorp_surf_for_resource()
245 aux_usage = ISL_AUX_USAGE_NONE; in iris_blorp_surf_for_resource()
257 .aux_usage = aux_usage, in iris_blorp_surf_for_resource()
260 if (aux_usage != ISL_AUX_USAGE_NONE) { in iris_blorp_surf_for_resource()
Diris_resource.c588 res->mod_info->aux_usage == ISL_AUX_USAGE_NONE || in iris_resource_configure_aux()
589 res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E || in iris_resource_configure_aux()
590 res->mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || in iris_resource_configure_aux()
591 res->mod_info->aux_usage == ISL_AUX_USAGE_MC); in iris_resource_configure_aux()
601 (res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE)) && in iris_resource_configure_aux()
619 res->aux.possible_usages |= 1 << res->mod_info->aux_usage; in iris_resource_configure_aux()
669 return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE; in iris_resource_configure_aux()
1126 mod ? mod->aux_usage : ISL_AUX_USAGE_NONE, in iris_flush_resource()
1136 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE; in iris_resource_disable_aux_on_first_query()
1163 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE; in iris_resource_get_param()
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Diris_clear.c376 enum isl_aux_usage aux_usage = in clear_color() local
380 box->z, box->depth, aux_usage); in clear_color()
385 p_res, aux_usage, level, true); in clear_color()
409 box->z, box->depth, aux_usage); in clear_color()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_mipmap_tree.c76 assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E); in format_ccs_e_compat_with_miptree()
168 assert(mt->aux_usage == ISL_AUX_USAGE_NONE); in intel_miptree_choose_aux_usage()
172 mt->aux_usage = ISL_AUX_USAGE_MCS; in intel_miptree_choose_aux_usage()
175 mt->aux_usage = ISL_AUX_USAGE_CCS_E; in intel_miptree_choose_aux_usage()
177 mt->aux_usage = ISL_AUX_USAGE_CCS_D; in intel_miptree_choose_aux_usage()
180 mt->aux_usage = ISL_AUX_USAGE_HIZ; in intel_miptree_choose_aux_usage()
186 if (mt->aux_usage != ISL_AUX_USAGE_NONE) in intel_miptree_choose_aux_usage()
567 if (mt->aux_usage != ISL_AUX_USAGE_CCS_D && in intel_miptree_create()
569 mt->aux_usage = ISL_AUX_USAGE_NONE; in intel_miptree_create()
655 if (mt->aux_usage != ISL_AUX_USAGE_CCS_D && in intel_miptree_create_for_bo()
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Dbrw_blorp.c122 enum isl_aux_usage aux_usage, in blorp_surf_for_miptree() argument
150 .aux_usage = aux_usage, in blorp_surf_for_miptree()
155 if (surf->aux_usage == ISL_AUX_USAGE_HIZ && in blorp_surf_for_miptree()
157 surf->aux_usage = ISL_AUX_USAGE_NONE; in blorp_surf_for_miptree()
159 if (surf->aux_usage != ISL_AUX_USAGE_NONE) { in blorp_surf_for_miptree()
182 assert((surf->aux_usage == ISL_AUX_USAGE_NONE) == in blorp_surf_for_miptree()
186 gen9_apply_single_tex_astc5x5_wa(brw, mt->format, surf->aux_usage); in blorp_surf_for_miptree()
461 switch (src_mt->aux_usage) { in brw_blorp_copy_miptrees()
464 src_aux_usage = src_mt->aux_usage; in brw_blorp_copy_miptrees()
473 src_aux_usage = src_mt->aux_usage; in brw_blorp_copy_miptrees()
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Dbrw_draw.c389 if (tex_mt->aux_usage != ISL_AUX_USAGE_CCS_D && in intel_disable_rb_aux_buffer()
390 tex_mt->aux_usage != ISL_AUX_USAGE_CCS_E) in intel_disable_rb_aux_buffer()
450 gen9_astc5x5_wa_bits(mesa_format format, enum isl_aux_usage aux_usage) in gen9_astc5x5_wa_bits() argument
452 if (aux_usage != ISL_AUX_USAGE_NONE && in gen9_astc5x5_wa_bits()
453 aux_usage != ISL_AUX_USAGE_MCS) in gen9_astc5x5_wa_bits()
469 enum isl_aux_usage aux_usage) in gen9_apply_single_tex_astc5x5_wa() argument
471 gen9_apply_astc5x5_wa_flush(brw, gen9_astc5x5_wa_bits(format, aux_usage)); in gen9_apply_single_tex_astc5x5_wa()
531 tex_obj->mt->aux_usage); in brw_predraw_resolve_inputs()
678 enum isl_aux_usage aux_usage = in brw_predraw_resolve_framebuffer() local
682 if (brw->draw_aux_usage[i] != aux_usage) { in brw_predraw_resolve_framebuffer()
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Dintel_mipmap_tree.h258 enum isl_aux_usage aux_usage; member
547 enum isl_aux_usage aux_usage,
574 enum isl_aux_usage aux_usage);
640 enum isl_aux_usage aux_usage);
645 enum isl_aux_usage aux_usage);
Dintel_fbo.h241 enum isl_aux_usage aux_usage);
245 enum isl_aux_usage aux_usage);
Dintel_fbo.c1045 format_aux_tuple(enum isl_format format, enum isl_aux_usage aux_usage) in format_aux_tuple() argument
1047 return (void *)(uintptr_t)((uint32_t)format << 8 | aux_usage); in format_aux_tuple()
1053 enum isl_aux_usage aux_usage) in brw_cache_flush_for_render() argument
1082 if (entry && entry->data != format_aux_tuple(format, aux_usage)) in brw_cache_flush_for_render()
1089 enum isl_aux_usage aux_usage) in brw_render_cache_add_bo() argument
1097 assert(entry->data == format_aux_tuple(format, aux_usage)); in brw_render_cache_add_bo()
1102 format_aux_tuple(format, aux_usage)); in brw_render_cache_add_bo()
Dbrw_wm_surface_state.c140 enum isl_aux_usage aux_usage, in brw_emit_surface_state() argument
161 if (aux_usage != ISL_AUX_USAGE_NONE) { in brw_emit_surface_state()
181 .aux_surf = aux_surf, .aux_usage = aux_usage, in brw_emit_surface_state()
613 enum isl_aux_usage aux_usage = in brw_update_texture_surface() local
617 brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, in brw_update_texture_surface()
1120 enum isl_aux_usage aux_usage = in update_renderbuffer_read_surfaces() local
1124 aux_usage = ISL_AUX_USAGE_NONE; in update_renderbuffer_read_surfaces()
1126 brw_emit_surface_state(brw, irb->mt, target, view, aux_usage, in update_renderbuffer_read_surfaces()
DgenX_blorp_exec.c317 params->dst.aux_usage); in genX()
405 params->dst.aux_usage); in genX()
/external/mesa3d/src/intel/vulkan/
Danv_image.c296 assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_NONE && in add_aux_state_tracking_buffer()
323 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) { in add_aux_state_tracking_buffer()
410 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ; in add_aux_surface_if_supported()
423 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ_CCS_WT; in add_aux_surface_if_supported()
426 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ_CCS; in add_aux_surface_if_supported()
438 image->planes[plane].aux_usage = ISL_AUX_USAGE_STC_CCS; in add_aux_surface_if_supported()
506 image->planes[plane].aux_usage = ISL_AUX_USAGE_CCS_E; in add_aux_surface_if_supported()
514 image->planes[plane].aux_usage = ISL_AUX_USAGE_CCS_D; in add_aux_surface_if_supported()
529 image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS; in add_aux_surface_if_supported()
599 image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE; in make_surface()
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Danv_blorp.c203 enum isl_aux_usage aux_usage, in get_blorp_surf_for_anv_image() argument
210 aux_usage = anv_layout_to_aux_usage(&device->info, image, in get_blorp_surf_for_anv_image()
228 if (aux_usage != ISL_AUX_USAGE_NONE) { in get_blorp_surf_for_anv_image()
236 blorp_surf->aux_usage = aux_usage; in get_blorp_surf_for_anv_image()
352 dst_surf.aux_usage, dst_level, in copy_image()
388 dst_surf.aux_usage, dst_level, in copy_image()
593 aspect, dst->surf.aux_usage, in copy_buffer_to_image()
851 dst.aux_usage, in blit_image()
1224 surf.aux_usage, level, in anv_CmdClearColorImage()
1737 assert(surf.aux_usage == ISL_AUX_USAGE_NONE); in anv_image_copy_to_shadow()
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DgenX_cmd_buffer.c542 if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage)) in anv_image_init_aux_tt()
568 if (image->planes[depth_plane].aux_usage == ISL_AUX_USAGE_NONE) in transition_depth_buffer()
676 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE) in transition_stencil_buffer()
735 if (image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_E) in set_image_compressed_bit()
925 image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_D) in anv_cmd_predicated_ccs_resolve()
961 enum isl_aux_usage aux_usage, in genX()
974 if (aux_usage != ISL_AUX_USAGE_CCS_E && in genX()
975 aux_usage != ISL_AUX_USAGE_MCS) in genX()
1253 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) { in transition_color_buffer()
1476 att_state->aux_usage = ISL_AUX_USAGE_NONE; in genX()
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Danv_genX.h86 enum isl_aux_usage aux_usage,
/external/mesa3d/src/intel/blorp/
Dblorp.c98 info->aux_usage = surf->aux_usage; in brw_blorp_surface_info_init()
99 if (info->aux_usage != ISL_AUX_USAGE_NONE) { in brw_blorp_surface_info_init()
149 assert(info->aux_usage == ISL_AUX_USAGE_NONE); in brw_blorp_surface_info_init()
Dblorp_blit.c1574 assert(info->aux_usage == ISL_AUX_USAGE_NONE); in blorp_surf_convert_to_single_slice()
1847 wm_prog_key->tex_aux_usage = params->src.aux_usage; in try_blorp_blit()
2662 assert(params.src.aux_usage == ISL_AUX_USAGE_NONE || in blorp_copy()
2663 params.src.aux_usage == ISL_AUX_USAGE_HIZ || in blorp_copy()
2664 params.src.aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || in blorp_copy()
2665 params.src.aux_usage == ISL_AUX_USAGE_MCS || in blorp_copy()
2666 params.src.aux_usage == ISL_AUX_USAGE_MCS_CCS || in blorp_copy()
2667 params.src.aux_usage == ISL_AUX_USAGE_CCS_E || in blorp_copy()
2668 params.src.aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || in blorp_copy()
2669 params.src.aux_usage == ISL_AUX_USAGE_STC_CCS); in blorp_copy()
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Dblorp_genX_exec.h1416 if (isl_aux_usage_has_hiz(surface->aux_usage)) { in blorp_emit_surface_state()
1422 enum isl_aux_usage aux_usage = surface->aux_usage; in blorp_emit_surface_state() local
1441 .aux_surf = &surface->aux_surf, .aux_usage = aux_usage, in blorp_emit_surface_state()
1444 .aux_address = aux_usage == ISL_AUX_USAGE_NONE ? 0 : in blorp_emit_surface_state()
1457 if (aux_usage != ISL_AUX_USAGE_NONE) { in blorp_emit_surface_state()
1468 if (aux_usage != ISL_AUX_USAGE_NONE && surface->clear_color_addr.buffer) { in blorp_emit_surface_state()
1639 info.hiz_usage = params->depth.aux_usage; in blorp_emit_depth_stencil_config()
1668 info.stencil_aux_usage = params->stencil.aux_usage; in blorp_emit_depth_stencil_config()
1812 assert(params->stencil.aux_usage == ISL_AUX_USAGE_STC_CCS); in blorp_emit_gen8_hiz_op()
Dblorp.h107 enum isl_aux_usage aux_usage; member
192 enum isl_aux_usage aux_usage,
Dblorp_priv.h56 enum isl_aux_usage aux_usage; member

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