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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td231 def : TLBI<"IPAS2E1IS", 0b01, 0b100, 0b1000, 0b0000, 0b001>;
232 def : TLBI<"IPAS2LE1IS", 0b01, 0b100, 0b1000, 0b0000, 0b101>;
312 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
313 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
314 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
319 def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
320 def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
321 def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;
322 def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;
323 def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>;
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td407 def : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>;
408 def : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>;
475 def : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
476 def : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>;
559 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
560 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
561 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
566 def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
567 def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
570 def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td402 def : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>;
403 def : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>;
470 def : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
471 def : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>;
554 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
555 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
556 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
561 def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
562 def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
565 def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
[all …]
DAArch64SVEInstrInfo.td193 defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd", int_aarch64_sve_fadd>;
313 defm AND_PPzPP : sve_int_pred_log<0b0000, "and", int_aarch64_sve_and_z>;
342 defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>;
388 defm LD1B : sve_mem_cld_ss<0b0000, "ld1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
406 defm LDNF1B_IMM : sve_mem_cldnf_si<0b0000, "ldnf1b", Z_b, ZPR8>;
424 defm LDFF1B : sve_mem_cldff_ss<0b0000, "ldff1b", Z_b, ZPR8, GPR64shifted8>;
471 …defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", AArch64ld1s_gather_sxtw, AAr…
493 …defm GLD1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0000, "ld1sb", imm0_31, AArch64ld1s_gather_imm, …
506 …defm GLD1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0000, "ld1sb", imm0_31, AArch64ld1s_gather_imm, …
523 defm GLD1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb", AArch64ld1s_gather, nxv2i8>;
[all …]
/external/vboot_reference/tests/futility/
Ddata_fmap2_expect_hhH.txt22 001b0000 001af000 fffff000 // gap in WP_RO
23 RO_VPD 001a0000 001b0000 00010000
26 GBB 000b0000 0019f000 000ef000
27 RO_FRID 000aff00 000b0000 00000100
Ddata_fmap2_expect_hh.txt20 RO_VPD 001a0000 001b0000 00010000
22 GBB 000b0000 0019f000 000ef000
23 RO_FRID 000aff00 000b0000 00000100
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td249 let Inst{31-16} = { 0b00011110, src1{1-0}, 0b0000, opc{4-3} };
311 class V6_vL32b_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0000>;
330 class V6_vL32b_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0000>;
360 class V6_vS32b_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b0000>;
364 class V6_vS32b_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b0000>;
454 class V6_vS32b_new_pred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b0000>;
471 class V6_vS32b_new_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b0000>;
489 class V6_vL32b_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0000>;
508 class V6_vL32b_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0000>;
530 class V6_vS32b_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b0000>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrFormats.td79 let rs = 0b0000;
135 let rs = 0b0000;
206 let rs = 0b0000;
263 let rs = 0b0000;
352 let rs = 0b0000;
398 let rs = 0b0000;
/external/llvm-project/llvm/lib/Target/MSP430/
DMSP430InstrFormats.td79 let rs = 0b0000;
135 let rs = 0b0000;
206 let rs = 0b0000;
263 let rs = 0b0000;
352 let rs = 0b0000;
398 let rs = 0b0000;
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td546 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
551 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
560 def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0,
570 let Inst{3-0} = 0b0000;
578 let Inst{3-0} = 0b0000;
590 let Inst{3-0} = 0b0000;
599 let Inst{3-0} = 0b0000;
607 let Inst{3-0} = 0b0000;
619 let Inst{3-0} = 0b0000;
962 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
[all …]
DARMInstrThumb2.td889 let Inst{7-4} = 0b0000;
1086 let Inst{26-23} = 0b0000;
1106 let Inst{26-23} = 0b0000;
1870 let Inst{7-4} = 0b0000;
2160 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2161 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2162 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2163 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2164 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2165 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMicroMipsDSPInstrFormats.td226 let Inst{25-22} = 0b0000;
229 let Inst{13-10} = 0b0000;
/external/llvm/lib/Target/Mips/
DMicroMipsDSPInstrFormats.td227 let Inst{25-22} = 0b0000;
230 let Inst{13-10} = 0b0000;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsDSPInstrFormats.td226 let Inst{25-22} = 0b0000;
229 let Inst{13-10} = 0b0000;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td593 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
598 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
607 def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0,
617 let Inst{3-0} = 0b0000;
625 let Inst{3-0} = 0b0000;
637 let Inst{3-0} = 0b0000;
645 let Inst{3-0} = 0b0000;
653 let Inst{3-0} = 0b0000;
665 let Inst{3-0} = 0b0000;
1042 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
[all …]
DARMInstrThumb2.td1082 let Inst{7-4} = 0b0000;
1285 let Inst{26-23} = 0b0000;
1306 let Inst{26-23} = 0b0000;
2065 let Inst{7-4} = 0b0000;
2463 def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>;
2464 def t2SADD16 : T2I_pam_intrinsics<0b001, 0b0000, "sadd16", int_arm_sadd16>;
2465 def t2SADD8 : T2I_pam_intrinsics<0b000, 0b0000, "sadd8", int_arm_sadd8>;
2466 def t2SSAX : T2I_pam_intrinsics<0b110, 0b0000, "ssax", int_arm_ssax>;
2467 def t2SSUB16 : T2I_pam_intrinsics<0b101, 0b0000, "ssub16", int_arm_ssub16>;
2468 def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>;
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td628 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
633 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
642 def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0,
652 let Inst{3-0} = 0b0000;
660 let Inst{3-0} = 0b0000;
672 let Inst{3-0} = 0b0000;
680 let Inst{3-0} = 0b0000;
688 let Inst{3-0} = 0b0000;
700 let Inst{3-0} = 0b0000;
1111 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
[all …]
DARMInstrThumb2.td1083 let Inst{7-4} = 0b0000;
1286 let Inst{26-23} = 0b0000;
1307 let Inst{26-23} = 0b0000;
2114 let Inst{7-4} = 0b0000;
2512 def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>;
2513 def t2SADD16 : T2I_pam_intrinsics<0b001, 0b0000, "sadd16", int_arm_sadd16>;
2514 def t2SADD8 : T2I_pam_intrinsics<0b000, 0b0000, "sadd8", int_arm_sadd8>;
2515 def t2SSAX : T2I_pam_intrinsics<0b110, 0b0000, "ssax", int_arm_ssax>;
2516 def t2SSUB16 : T2I_pam_intrinsics<0b101, 0b0000, "ssub16", int_arm_ssub16>;
2517 def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>;
[all …]
/external/python/cpython3/Tools/pynche/
Dwebcolors.txt33 DarkRed #8b0000
/external/python/cpython2/Tools/pynche/
Dwebcolors.txt33 DarkRed #8b0000
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt87 # The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
177 # To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1…
195 # To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b110…
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt87 # The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
200 # To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1…
218 # To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b110…
/external/arm-trusted-firmware/fdts/
Dfvp-foundation-motherboard.dtsi79 v2m_serial2: uart@b0000 {
Drtsm_ve-motherboard.dtsi127 v2m_serial2: uart@b0000 {
Drtsm_ve-motherboard-aarch32.dtsi128 v2m_serial2: uart@b0000 {

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