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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td462 def : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>;
463 def : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>;
464 def : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>;
465 def : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>;
478 def : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>;
479 def : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>;
484 def : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>;
485 def : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>;
585 def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>;
586 def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>;
[all …]
DAArch64SVEInstrInfo.td195 defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul", int_aarch64_sve_fmul>;
315 defm EOR_PPzPP : sve_int_pred_log<0b0010, "eor", int_aarch64_sve_eor_z>;
344 defm LD1B_S_IMM : sve_mem_cld_si<0b0010, "ld1b", Z_s, ZPR32>;
390 defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64NoXZRshifted8>;
408 defm LDNF1B_S_IMM : sve_mem_cldnf_si<0b0010, "ldnf1b", Z_s, ZPR32>;
426 defm LDFF1B_S : sve_mem_cldff_ss<0b0010, "ldff1b", Z_s, ZPR32, GPR64shifted8>;
473 …defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", AArch64ld1_gather_sxtw, AAr…
495 …defm GLD1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b", imm0_31, AArch64ld1_gather_imm, …
508 …defm GLD1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b", imm0_31, AArch64ld1_gather_imm, …
525 defm GLD1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0010, "ld1b", AArch64ld1_gather, nxv2i8>;
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/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td467 def : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>;
468 def : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>;
469 def : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>;
470 def : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>;
483 def : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>;
484 def : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>;
489 def : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>;
490 def : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>;
590 def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>;
591 def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>;
[all …]
DAArch64SVEInstrInfo.td411 …defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul", "FMUL_ZPZZ", int_aarch64_sve_fmul, Destructive…
643 defm EOR_PPzPP : sve_int_pred_log<0b0010, "eor", int_aarch64_sve_eor_z, xor>;
684 defm LD1B_S_IMM : sve_mem_cld_si<0b0010, "ld1b", Z_s, ZPR32>;
730 defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64NoXZRshifted8>;
748 defm LDNF1B_S_IMM : sve_mem_cldnf_si<0b0010, "ldnf1b", Z_s, ZPR32>;
766 defm LDFF1B_S : sve_mem_cldff_ss<0b0010, "ldff1b", Z_s, ZPR32, GPR64shifted8>;
813 …defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", AArch64ld1_gather_sxtw_z, A…
835 …defm GLD1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b", imm0_31, AArch64ld1_gather_imm_z, …
848 …defm GLD1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b", imm0_31, AArch64ld1_gather_imm_z, …
865 …defm GLD1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0010, "ld1b", AArch64ld1_gather_z, nxv2i…
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td335 def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>;
336 def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>;
337 def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>;
338 def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>;
339 def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>;
340 def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>;
363 def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>;
370 def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>;
389 def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>;
458 def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>;
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/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp129 b0010 = 0x2, enumerator
151 { true, false, false, b0010, b0010, b1101, false, NONE },
154 { true, true, true, b0010, b1000, b0001, false, NONE },
156 { true, true, true, b0010, b1000, b1111, true, FILL },
159 { true, true, true, b0010, b1000, b1111, true, COPY },
/external/llvm/test/TableGen/
DBitsInit.td42 let E{3-0} = 0b0010;
/external/llvm-project/llvm/test/TableGen/
DBitsInit.td42 let E{3...0} = 0b0010;
DDAGDefaultOps.td63 def SubRRI : RRI<"sub", 0b0010> {
/external/llvm-project/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h109 TTT = 0b0010,
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td313 class V6_vL32b_tmp_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0010>;
332 class V6_vL32b_tmp_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0010>;
491 class V6_vL32b_tmp_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0010>;
510 class V6_vL32b_tmp_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0010>;
821 class V6_vasrwh_enc : Enc_COPROC_VX_4op_r<0b0010>;
/external/llvm-project/llvm/lib/Target/RISCV/Utils/
DRISCVBaseInfo.h58 VS1Constraint = 0b0010,
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td274 defm : int_cond_alias<"le", 0b0010>;
301 defm : fp_cond_alias<"lg", 0b0010>;
324 defm : cp_cond_alias<"12", 0b0010>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td273 defm : int_cond_alias<"le", 0b0010>;
300 defm : fp_cond_alias<"lg", 0b0010>;
323 defm : cp_cond_alias<"12", 0b0010>;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td273 defm : int_cond_alias<"le", 0b0010>;
300 defm : fp_cond_alias<"lg", 0b0010>;
323 defm : cp_cond_alias<"12", 0b0010>;
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td569 def ANDRdRr : FRdRr<0b0010,
588 def ORRdRr : FRdRr<0b0010,
607 def EORRdRr : FRdRr<0b0010,
702 def TSTRd : FTST<0b0010,
1049 def MOVRdRr : FRdRr<0b0010,
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt288 # VLD1 multi-element type=0b0010 align=0b1x
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td1867 let Inst{24-21} = 0b0010;
1887 let Inst{24-21} = 0b0010;
1911 let Inst{24-21} = 0b0010;
2175 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2176 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2177 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2178 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2179 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2180 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2312 let Inst{24-21} = 0b0010;
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/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrFormats.td57 def VS1Constraint : RISCVVConstraint<0b0010>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td754 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1);
769 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); // see above
2061 let Inst{24-21} = 0b0010;
2082 let Inst{24-21} = 0b0010;
2106 let Inst{24-21} = 0b0010;
2478 def t2SHASX : T2I_pam_intrinsics<0b010, 0b0010, "shasx", int_arm_shasx>;
2479 def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>;
2480 def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>;
2481 def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>;
2482 def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>;
[all …]
DARMInstrVFP.td713 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
735 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
747 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
791 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
2371 : MovFromVFP<0b0010 /* fpscr_nzcvqc */,
2453 : MovToVFP<0b0010 /* fpscr_nzcvqc */,
2734 defm VSTR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b0,0b0010, "fpscr_nzcvqc">;
2752 defm VLDR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b1,0b0010, "fpscr_nzcvqc">;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td755 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1);
770 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); // see above
2110 let Inst{24-21} = 0b0010;
2131 let Inst{24-21} = 0b0010;
2155 let Inst{24-21} = 0b0010;
2527 def t2SHASX : T2I_pam_intrinsics<0b010, 0b0010, "shasx", int_arm_shasx>;
2528 def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>;
2529 def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>;
2530 def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>;
2531 def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>;
[all …]
DARMInstrVFP.td751 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
781 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
808 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
856 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
2467 : MovFromVFP<0b0010 /* fpscr_nzcvqc */,
2549 : MovToVFP<0b0010 /* fpscr_nzcvqc */,
2835 defm VSTR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b0,0b0010, "fpscr_nzcvqc">;
2859 defm VLDR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b1,0b0010, "fpscr_nzcvqc">;
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td589 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
590 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
591 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
592 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
640 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
641 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
670 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
671 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
726 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
727 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt288 # VLD1 multi-element type=0b0010 align=0b1x

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