Home
last modified time | relevance | path

Searched refs:b0011 (Results 1 – 25 of 56) sorted by relevance

123

/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td233 def : TLBI<"VMALLE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b000, 0>;
234 def : TLBI<"ALLE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b000, 0>;
235 def : TLBI<"ALLE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b000, 0>;
236 def : TLBI<"VAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b001>;
237 def : TLBI<"VAE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b001>;
238 def : TLBI<"VAE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b001>;
239 def : TLBI<"ASIDE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b010>;
240 def : TLBI<"VAAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b011>;
241 def : TLBI<"ALLE1IS", 0b01, 0b100, 0b1000, 0b0011, 0b100, 0>;
242 def : TLBI<"VALE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b101>;
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td409 def : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>;
410 def : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>;
411 def : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>;
412 def : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>;
413 def : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>;
414 def : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>;
415 def : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
416 def : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>;
417 def : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>;
418 def : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>;
[all …]
DAArch64SVEInstrInfo.td412 …defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr", "FSUBR_ZPZZ", int_aarch64_sve_fsubr, Destruct…
644 defm SEL_PPPP : sve_int_pred_log<0b0011, "sel", vselect>;
685 defm LD1B_D_IMM : sve_mem_cld_si<0b0011, "ld1b", Z_d, ZPR64>;
731 defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64NoXZRshifted8>;
749 defm LDNF1B_D_IMM : sve_mem_cldnf_si<0b0011, "ldnf1b", Z_d, ZPR64>;
767 defm LDFF1B_D : sve_mem_cldff_ss<0b0011, "ldff1b", Z_d, ZPR64, GPR64shifted8>;
814 …defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", AArch64ldff1_gather_sxtw_z, A…
836 …defm GLDFF1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b", imm0_31, AArch64ldff1_gather_imm_z…
849 …defm GLDFF1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b", imm0_31, AArch64ldff1_gather_imm_z…
866 …defm GLDFF1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0011, "ldff1b", AArch64ldff1_gather_z, nxv2i…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td404 def : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>;
405 def : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>;
406 def : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>;
407 def : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>;
408 def : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>;
409 def : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>;
410 def : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
411 def : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>;
412 def : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>;
413 def : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>;
[all …]
DAArch64SVEInstrInfo.td196 defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr", int_aarch64_sve_fsubr>;
316 defm SEL_PPPP : sve_int_pred_log<0b0011, "sel", vselect>;
345 defm LD1B_D_IMM : sve_mem_cld_si<0b0011, "ld1b", Z_d, ZPR64>;
391 defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64NoXZRshifted8>;
409 defm LDNF1B_D_IMM : sve_mem_cldnf_si<0b0011, "ldnf1b", Z_d, ZPR64>;
427 defm LDFF1B_D : sve_mem_cldff_ss<0b0011, "ldff1b", Z_d, ZPR64, GPR64shifted8>;
474 …defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", null_frag, nul…
496 …defm GLDFF1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b", imm0_31, null_frag, …
509 …defm GLDFF1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b", imm0_31, null_frag, …
526 defm GLDFF1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0011, "ldff1b", null_frag, nxv2i8>;
[all …]
/external/mesa3d/src/panfrost/midgard/
Dmidgard_derivatives.c135 bool lower = ins->mask & 0b0011; in midgard_lower_derivatives()
146 ins->mask &= 0b0011; in midgard_lower_derivatives()
/external/llvm-project/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h114 TTTE = 0b0011,
/external/mesa3d/src/panfrost/bifrost/
Dbifrost.h315 #define BIFROST_FMTC_CONSTANTS 0b0011
/external/llvm-project/llvm/test/TableGen/
DDAGDefaultOps.td67 def MulRRI : RRI<"mul", 0b0011> {
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td276 defm : int_cond_alias<"l", 0b0011>;
300 defm : fp_cond_alias<"ul", 0b0011>;
323 defm : cp_cond_alias<"13", 0b0011>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td275 defm : int_cond_alias<"l", 0b0011>;
299 defm : fp_cond_alias<"ul", 0b0011>;
322 defm : cp_cond_alias<"13", 0b0011>;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td275 defm : int_cond_alias<"l", 0b0011>;
299 defm : fp_cond_alias<"ul", 0b0011>;
322 defm : cp_cond_alias<"13", 0b0011>;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV3.td101 : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
DHexagonInstrInfoV4.td261 let Inst{27-24} = 0b0011;
302 let Inst{27-24} = 0b0011;
425 def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
483 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
547 let IClass = 0b0011;
579 let IClass = 0b0011;
869 let IClass = 0b0011;
904 let IClass = 0b0011;
933 let IClass = 0b0011;
964 let IClass = 0b0011;
[all …]
DHexagonInstrInfo.td682 let Inst{27-24} = 0b0011;
868 let Inst{27-24} = 0b0011;
989 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
1289 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1300 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1745 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1944 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
2019 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
2082 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
2166 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td838 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
840 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
842 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
876 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
878 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
880 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
1290 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1331 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1825 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1827 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
[all …]
DARMInstrVFP.td672 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
682 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
699 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
726 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td819 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
821 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
823 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
857 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
859 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
861 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
1298 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1339 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1884 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1886 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td795 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
797 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
799 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
833 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
835 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
837 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
1280 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1321 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1866 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1868 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
[all …]
DARMInstrVFP.td763 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
795 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
831 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
870 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
1974 let Inst{19-16} = 0b0011; // opcode3
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td594 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
595 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
596 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
652 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
653 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
658 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
659 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
673 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
674 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
/external/llvm-project/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td608 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
609 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
610 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
666 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
667 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
672 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
673 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
687 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
688 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td608 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
609 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
610 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
666 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
667 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
672 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
673 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
687 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
688 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td452 let imm12 = {0b1000,0b0011,0b0011};
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoB.td523 def : InstAlias<"zip.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0011)>,
525 def : InstAlias<"unzip.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0011)>,

123