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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td169 def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>;
170 def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>;
466 def : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>;
467 def : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>;
468 def : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>;
469 def : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>;
480 def : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>;
481 def : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>;
486 def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;
487 def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;
[all …]
DAArch64SVEInstrInfo.td198 defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm", int_aarch64_sve_fminnm>;
318 defm BICS_PPzPP : sve_int_pred_log<0b0101, "bics", null_frag>;
347 defm LD1H_IMM : sve_mem_cld_si<0b0101, "ld1h", Z_h, ZPR16>;
393 defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
411 defm LDNF1H_IMM : sve_mem_cldnf_si<0b0101, "ldnf1h", Z_h, ZPR16>;
429 defm LDFF1H : sve_mem_cldff_ss<0b0101, "ldff1h", Z_h, ZPR16, GPR64shifted16>;
476 …defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", null_frag, nul…
485 …defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", null_frag, …
498 …defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2, null_frag, …
511 …defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2, null_frag, …
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td174 def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>;
175 def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>;
471 def : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>;
472 def : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>;
473 def : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>;
474 def : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>;
485 def : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>;
486 def : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>;
491 def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;
492 def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;
[all …]
DAArch64SVEInstrInfo.td414 …defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm", "FMINNM_ZPZZ", int_aarch64_sve_fminnm, Destr…
646 defm BICS_PPzPP : sve_int_pred_log<0b0101, "bics", null_frag>;
687 defm LD1H_IMM : sve_mem_cld_si<0b0101, "ld1h", Z_h, ZPR16>;
733 defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
751 defm LDNF1H_IMM : sve_mem_cldnf_si<0b0101, "ldnf1h", Z_h, ZPR16>;
769 defm LDFF1H : sve_mem_cldff_ss<0b0101, "ldff1h", Z_h, ZPR16, GPR64shifted16>;
816 …defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", AArch64ldff1s_gather_sxtw_z, A…
825 …defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", AArch64ldff1s_gather_sxtw_scaled…
838 …defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2, AArch64ldff1s_gather_imm_…
851 …defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2, AArch64ldff1s_gather_imm_…
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td122 def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>;
313 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
343 def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>;
344 def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>;
345 def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>;
346 def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>;
373 def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>;
383 def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>;
392 def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>;
423 def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>;
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/external/llvm/lib/Target/Hexagon/
DHexagonSystemInst.td84 let IClass = 0b0101;
108 let IClass = 0b0101;
125 let IClass = 0b0101;
DHexagonInstrInfoV3.td34 let IClass = 0b0101;
53 let IClass = 0b0101;
DHexagonInstrEnc.td455 class V6_vS32b_new_npred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b0101>;
472 class V6_vS32b_new_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b0101>;
642 class V6_vS32b_new_npred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b0101>;
659 class V6_vS32b_new_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b0101>;
737 class V6_vS32b_new_npred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b0101>;
824 class V6_vasrwuhsat_enc : Enc_COPROC_VX_4op_r<0b0101>;
DHexagonInstrInfo.td82 let Inst{27-24} = 0b0101;
991 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
1451 let IClass = 0b0101;
1473 let IClass = 0b0101;
1510 let IClass = 0b0101;
1529 let IClass = 0b0101;
1567 let IClass = 0b0101;
1749 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
1948 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
2023 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
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/external/llvm-project/clang/test/Lexer/
Dgnu-flags.c45 int b = 0b0101;
/external/clang/test/Lexer/
Dgnu-flags.c45 int b = 0b0101;
/external/llvm/test/TableGen/
Dlist-element-bitref.td10 def c0 : C<[0b0101, 0b1010]>;
/external/llvm-project/llvm/test/TableGen/
Dlist-element-bitref.td10 def c0 : C<[0b0101, 0b1010]>;
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPseudo.td171 let IClass = 0b0101;
193 let IClass = 0b0101;
227 let IClass = 0b0101;
287 let IClass = 0b0101;
344 let IClass = 0b0101;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td171 let IClass = 0b0101;
193 let IClass = 0b0101;
227 let IClass = 0b0101;
287 let IClass = 0b0101;
344 let IClass = 0b0101;
/external/llvm-project/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h116 TTET = 0b0101,
/external/starlark-go/starlark/testdata/
Dint.star156 assert.eq(int("0b0101", 0), 5)
157 assert.eq(int("0b0101", 2), 5) # prefix is redundant with explicit base
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td280 defm : int_cond_alias<"cs", 0b0101>;
292 defm : int_cond_alias<"lu", 0b0101>; // same as cs
298 defm : fp_cond_alias<"ug", 0b0101>;
321 defm : cp_cond_alias<"23", 0b0101>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td279 defm : int_cond_alias<"cs", 0b0101>;
291 defm : int_cond_alias<"lu", 0b0101>; // same as cs
297 defm : fp_cond_alias<"ug", 0b0101>;
320 defm : cp_cond_alias<"23", 0b0101>;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td279 defm : int_cond_alias<"cs", 0b0101>;
291 defm : int_cond_alias<"lu", 0b0101>; // same as cs
297 defm : fp_cond_alias<"ug", 0b0101>;
320 defm : cp_cond_alias<"23", 0b0101>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td942 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
943 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
944 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
945 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
946 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
947 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
1147 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1159 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1183 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1194 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
[all …]
DARMInstrVFP.td566 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
574 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
586 def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,
595 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
603 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
615 def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,
2092 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrFormatsV.td62 def LSWidth16 : RISCVWidth<0b0101>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td923 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
924 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
925 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
926 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
927 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
928 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
1154 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1166 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1190 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1201 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td899 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
900 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
901 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
902 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
903 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
904 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
1136 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1148 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1172 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1183 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
[all …]

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